Merge tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

power management changes for omap and imx

A significant part of the changes for these two platforms went into
power management, so they are split out into a separate branch.

* tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (65 commits)
  ARM: imx6: remove __CPUINIT annotation from v7_invalidate_l1
  ARM: imx6: fix v7_invalidate_l1 by adding I-Cache invalidation
  ARM: imx6q: resume PL310 only when CACHE_L2X0 defined
  ARM: imx6q: build pm code only when CONFIG_PM selected
  ARM: mx5: use generic irq chip pm interface for pm functions on
  ARM: omap: pass minimal SoC/board data for UART from dt
  arm/dts: Add minimal device tree support for omap2420 and omap2430
  omap-serial: Add minimal device tree support
  omap-serial: Use default clock speed (48Mhz) if not specified
  omap-serial: Get rid of all pdev->id usage
  ARM: OMAP2+: hwmod: Add a new flag to handle hwmods left enabled at init
  ARM: OMAP4: PRM: use PRCM interrupt handler
  ARM: OMAP3: pm: use prcm chain handler
  ARM: OMAP: hwmod: add support for selecting mpu_irq for each wakeup pad
  ARM: OMAP2+: mux: add support for PAD wakeup interrupts
  ARM: OMAP: PRCM: add suspend prepare / finish support
  ARM: OMAP: PRCM: add support for chain interrupt handler
  ARM: OMAP3/4: PRM: add functions to read pending IRQs, PRM barrier
  ARM: OMAP2+: hwmod: Add API to enable IO ring wakeup
  ARM: OMAP2+: mux: add wakeup-capable hwmod mux entries to dynamic list
  ...

1 files changed, 21 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b7407154c881..904bd1dfcd2e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -365,6 +365,27 @@ config OMAP3_SDRC_AC_TIMING
           wish to say no.  Selecting yes without understanding what is
           going on could result in system crashes;
 
+config OMAP4_ERRATA_I688
+        bool "OMAP4 errata: Async Bridge Corruption"
+        depends on ARCH_OMAP4
+        select ARCH_HAS_BARRIERS
+        help
+          If a data is stalled inside asynchronous bridge because of back
+          pressure, it may be accepted multiple times, creating pointer
+          misalignment that will corrupt next transfers on that data path
+          until next reset of the system (No recovery procedure once the
+          issue is hit, the path remains consistently broken). Async bridge
+          can be found on path between MPU to EMIF and MPU to L3 interconnect.
+          This situation can happen only when the idle is initiated by a
+          Master Request Disconnection (which is trigged by software when
+          executing WFI on CPU).
+          The work-around for this errata needs all the initiators connected
+          through async bridge must ensure that data path is properly drained
+          before issuing WFI. This condition will be met if one Strongly ordered
+          access is performed to the target right before executing the WFI.
+          In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
+          IO barrier ensure that there is no synchronisation loss on initiators
+          operating on both interconnect port simultaneously.
 endmenu
 
 endif