Merge tag 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

New feature development

This adds support for new features, and contains stuff from most
platforms. A number of these patches could have fit into other
branches, too, but were small enough not to cause too much
confusion here.

* tag 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
  mfd/db8500-prcmu: remove support for early silicon revisions
  ARM: ux500: fix the smp_twd clock calculation
  ARM: ux500: remove support for early silicon revisions
  ARM: ux500: update register files
  ARM: ux500: register DB5500 PMU dynamically
  ARM: ux500: update ASIC detection for U5500
  ARM: ux500: support DB8520
  ARM: picoxcell: implement watchdog restart
  ARM: OMAP3+: hwmod data: Add the default clockactivity for I2C
  ARM: OMAP3: hwmod data: disable multiblock reads on MMC1/2 on OMAP34xx/35xx <= ES2.1
  ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP4
  ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP3
  ARM: OMAP: hwmod data: Add support for AM35xx UART4/ttyO3
  ARM: Orion: Remove address map info from all platform data structures
  ARM: Orion: Get address map from plat-orion instead of via platform_data
  ARM: Orion: mbus_dram_info consolidation
  ARM: Orion: Consolidate the address map setup
  ARM: Kirkwood: Add configuration for MPP12 as GPIO
  ARM: Kirkwood: Recognize A1 revision of 6282 chip
  ARM: ux500: update the MOP500 GPIO assignments
  ...

6 files changed, 49 insertions, 115 deletions

diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 73f287d6429b..4f8d66f044e7 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -168,70 +168,6 @@ config MACH_OMAP_GENERIC
           custom OMAP boards. Say Y here if you have a custom
           board.
 
-comment "OMAP CPU Speed"
-        depends on ARCH_OMAP1
-
-config OMAP_ARM_216MHZ
-        bool "OMAP ARM 216 MHz CPU (1710 only)"
-        depends on ARCH_OMAP1 && ARCH_OMAP16XX
-        help
-          Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N.
-
-config OMAP_ARM_195MHZ
-        bool "OMAP ARM 195 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 195MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_192MHZ
-        bool "OMAP ARM 192 MHz CPU"
-        depends on ARCH_OMAP1 && ARCH_OMAP16XX
-        help
-          Enable 192MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_182MHZ
-        bool "OMAP ARM 182 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 182MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_168MHZ
-        bool "OMAP ARM 168 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 168MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_150MHZ
-        bool "OMAP ARM 150 MHz CPU"
-        depends on ARCH_OMAP1 && ARCH_OMAP15XX
-        help
-          Enable 150MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_120MHZ
-        bool "OMAP ARM 120 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 120MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_96MHZ
-        bool "OMAP ARM 96 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 96MHz clock for OMAP CPU. If unsure, say N.
-
-config OMAP_ARM_60MHZ
-        bool "OMAP ARM 60 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        default y
-        help
-          Enable 60MHz clock for OMAP CPU. If unsure, say Y.
-
-config OMAP_ARM_30MHZ
-        bool "OMAP ARM 30 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 30MHz clock for OMAP CPU. If unsure, say N.
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 84ef70476b51..0c50df05d135 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -197,11 +197,10 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
         ref_rate = ck_ref_p->rate;
 
         for (ptr = omap1_rate_table; ptr->rate; ptr++) {
-                if (ptr->xtal != ref_rate)
+                if (!(ptr->flags & cpu_mask))
                         continue;
 
-                /* DPLL1 cannot be reprogrammed without risking system crash */
-                if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
+                if (ptr->xtal != ref_rate)
                         continue;
 
                 /* Can check only after xtal frequency check */
@@ -215,12 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
         /*
          * In most cases we should not need to reprogram DPLL.
          * Reprogramming the DPLL is tricky, it must be done from SRAM.
-         * (on 730, bit 13 must always be 1)
          */
-        if (cpu_is_omap7xx())
-                omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
-        else
-                omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
+        omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 
         /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
         ck_dpll1_p->rate = ptr->pll_rate;
@@ -290,6 +285,9 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
         highest_rate = -EINVAL;
 
         for (ptr = omap1_rate_table; ptr->rate; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
+
                 if (ptr->xtal != ref_rate)
                         continue;
 
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 16b1423b454a..3d04f4f67676 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -111,4 +111,7 @@ extern const struct clkops clkops_dummy;
 extern const struct clkops clkops_uart_16xx;
 extern const struct clkops clkops_generic;
 
+/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
+extern u32 cpu_mask;
+
 #endif
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 9ff90a744a21..94699a82a734 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,6 +25,7 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/clkdev_omap.h>
+#include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
 #include <plat/usb.h>   /* for OTG_BASE */
 
 #include "clock.h"
@@ -778,12 +779,14 @@ static void __init omap1_show_rates(void)
                 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 }
 
+u32 cpu_mask;
+
 int __init omap1_clk_init(void)
 {
         struct omap_clk *c;
         const struct omap_clock_config *info;
         int crystal_type = 0; /* Default 12 MHz */
-        u32 reg, cpu_mask;
+        u32 reg;
 
 #ifdef CONFIG_DEBUG_LL
         /*
@@ -808,6 +811,8 @@ int __init omap1_clk_init(void)
                 clk_preinit(c->lk.clk);
 
         cpu_mask = 0;
+        if (cpu_is_omap1710())
+                cpu_mask |= CK_1710;
         if (cpu_is_omap16xx())
                 cpu_mask |= CK_16XX;
         if (cpu_is_omap1510())
@@ -931,17 +936,13 @@ void __init omap1_clk_late_init(void)
 {
         unsigned long rate = ck_dpll1.rate;
 
-        if (rate >= OMAP1_DPLL1_SANE_VALUE)
-                return;
-
-        /* System booting at unusable rate, force reprogramming of DPLL1 */
-        ck_dpll1_p->rate = 0;
-
         /* Find the highest supported frequency and enable it */
         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
                 pr_err("System frequencies not set, using default. Check your config.\n");
-                omap_writew(0x2290, DPLL_CTL);
-                omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL);
+                /*
+                 * Reprogramming the DPLL is tricky, it must be done from SRAM.
+                 */
+                omap_sram_reprogram_clock(0x2290, 0x0005);
                 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
         }
         propagate_rate(&ck_dpll1);
diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h
index 07074d79adce..79a683864a5c 100644
--- a/arch/arm/mach-omap1/opp.h
+++ b/arch/arm/mach-omap1/opp.h
@@ -21,6 +21,7 @@ struct mpu_rate {
         unsigned long           pll_rate;
         __u16                   ckctl_val;
         __u16                   dpllctl_val;
+        u32                     flags;
 };
 
 extern struct mpu_rate omap1_rate_table[];
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
index 75a546514994..9cd4ddb51397 100644
--- a/arch/arm/mach-omap1/opp_data.c
+++ b/arch/arm/mach-omap1/opp_data.c
@@ -10,6 +10,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <plat/clkdev_omap.h>
 #include "opp.h"
 
 /*-------------------------------------------------------------------------
@@ -20,40 +21,34 @@ struct mpu_rate omap1_rate_table[] = {
          * NOTE: Comment order here is different from bits in CKCTL value:
          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
          */
-#if defined(CONFIG_OMAP_ARM_216MHZ)
-        { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_195MHZ)
-        { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_192MHZ)
-        { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
-        { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
-        {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
-        {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
-        {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_182MHZ)
-        { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_168MHZ)
-        { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_150MHZ)
-        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_120MHZ)
-        { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_96MHZ)
-        {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_60MHZ)
-        {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_30MHZ)
-        {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
-#endif
+        { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
+                        CK_1710 },
+        { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
+                        CK_7XX },
+        { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
+                        CK_16XX },
+        { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
+                        CK_16XX },
+        {  96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
+                        CK_16XX },
+        {  48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */
+                        CK_16XX },
+        {  24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */
+                        CK_16XX },
+        { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */
+                        CK_7XX },
+        { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */
+                        CK_16XX|CK_7XX },
+        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */
+                        CK_1510 },
+        { 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
+        {  96000000, 12000000,  96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
+        {  60000000, 12000000,  60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
+        {  30000000, 12000000,  60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
         { 0, 0, 0, 0, 0 },
 };