OMAP: DMA: Convert DMA library into platform driver

Convert DMA library into DMA platform driver and make use of
platform data provided by hwmod data base for OMAP2+ onwards.

For OMAP1 processors, the DMA driver in mach-omap uses resource
structures for getting platform data.

Thanks to Tony Lindgren <tony@atomide.com> for fixing various
omap1 issues and testing the same on OSK5912 board.

Signed-off-by: G, Manjunath Kondaiah <manjugk@ti.com>
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

2 files changed, 214 insertions, 3 deletions

diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 0b1c07ffa2f1..6ee19504845f 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o
+obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o
 obj-y += clock.o clock_data.o opp_data.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 120eff707ab2..d8559344c6e2 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -30,6 +30,57 @@
 #include <plat/irqs.h>
 
 #define OMAP1_DMA_BASE                  (0xfffed800)
+#define OMAP1_LOGICAL_DMA_CH_COUNT      17
+#define OMAP1_DMA_STRIDE                0x40
+
+static u32 errata;
+static u32 enable_1510_mode;
+static u8 dma_stride;
+static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+
+static u16 reg_map[] = {
+        [GCR]           = 0x400,
+        [GSCR]          = 0x404,
+        [GRST1]         = 0x408,
+        [HW_ID]         = 0x442,
+        [PCH2_ID]       = 0x444,
+        [PCH0_ID]       = 0x446,
+        [PCH1_ID]       = 0x448,
+        [PCHG_ID]       = 0x44a,
+        [PCHD_ID]       = 0x44c,
+        [CAPS_0]        = 0x44e,
+        [CAPS_1]        = 0x452,
+        [CAPS_2]        = 0x456,
+        [CAPS_3]        = 0x458,
+        [CAPS_4]        = 0x45a,
+        [PCH2_SR]       = 0x460,
+        [PCH0_SR]       = 0x480,
+        [PCH1_SR]       = 0x482,
+        [PCHD_SR]       = 0x4c0,
+
+        /* Common Registers */
+        [CSDP]          = 0x00,
+        [CCR]           = 0x02,
+        [CICR]          = 0x04,
+        [CSR]           = 0x06,
+        [CEN]           = 0x10,
+        [CFN]           = 0x12,
+        [CSFI]          = 0x14,
+        [CSEI]          = 0x16,
+        [CPC]           = 0x18, /* 15xx only */
+        [CSAC]          = 0x18,
+        [CDAC]          = 0x1a,
+        [CDEI]          = 0x1c,
+        [CDFI]          = 0x1e,
+        [CLNK_CTRL]     = 0x28,
+
+        /* Channel specific register offsets */
+        [CSSA]          = 0x08,
+        [CDSA]          = 0x0c,
+        [COLOR]         = 0x20,
+        [CCR2]          = 0x24,
+        [LCH_CTRL]      = 0x2a,
+};
 
 static struct resource res[] __initdata = {
         [0] = {
@@ -67,6 +118,7 @@ static struct resource res[] __initdata = {
                 .start  = INT_DMA_CH5,
                 .flags  = IORESOURCE_IRQ,
         },
+        /* Handled in lcd_dma.c */
         [7] = {
                 .name   = "6",
                 .start  = INT_1610_DMA_CH6,
@@ -125,9 +177,100 @@ static struct resource res[] __initdata = {
         },
 };
 
+static void __iomem *dma_base;
+static inline void dma_write(u32 val, int reg, int lch)
+{
+        u8  stride;
+        u32 offset;
+
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+
+        __raw_writew(val, dma_base + offset);
+        if ((reg > CLNK_CTRL && reg < CCEN) ||
+                        (reg > PCHD_ID && reg < CAPS_2)) {
+                u32 offset2 = reg_map[reg] + 2 + (stride * lch);
+                __raw_writew(val >> 16, dma_base + offset2);
+        }
+}
+
+static inline u32 dma_read(int reg, int lch)
+{
+        u8 stride;
+        u32 offset, val;
+
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+
+        val = __raw_readw(dma_base + offset);
+        if ((reg > CLNK_CTRL && reg < CCEN) ||
+                        (reg > PCHD_ID && reg < CAPS_2)) {
+                u16 upper;
+                u32 offset2 = reg_map[reg] + 2 + (stride * lch);
+                upper = __raw_readw(dma_base + offset2);
+                val |= (upper << 16);
+        }
+        return val;
+}
+
+static void omap1_clear_lch_regs(int lch)
+{
+        int i = dma_common_ch_start;
+
+        for (; i <= dma_common_ch_end; i += 1)
+                dma_write(0, i, lch);
+}
+
+static void omap1_clear_dma(int lch)
+{
+        u32 l;
+
+        l = dma_read(CCR, lch);
+        l &= ~OMAP_DMA_CCR_EN;
+        dma_write(l, CCR, lch);
+
+        /* Clear pending interrupts */
+        l = dma_read(CSR, lch);
+}
+
+static void omap1_show_dma_caps(void)
+{
+        if (enable_1510_mode) {
+                printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
+        } else {
+                u16 w;
+                printk(KERN_INFO "OMAP DMA hardware version %d\n",
+                                                        dma_read(HW_ID, 0));
+                printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
+                        dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
+                        dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
+                        dma_read(CAPS_4, 0));
+
+                /* Disable OMAP 3.0/3.1 compatibility mode. */
+                w = dma_read(GSCR, 0);
+                w |= 1 << 3;
+                dma_write(w, GSCR, 0);
+        }
+        return;
+}
+
+static u32 configure_dma_errata(void)
+{
+
+        /*
+         * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        if (!cpu_is_omap15xx())
+                SET_DMA_ERRATA(DMA_ERRATA_3_3);
+
+        return errata;
+}
+
 static int __init omap1_system_dma_init(void)
 {
         struct omap_system_dma_plat_info        *p;
+        struct omap_dma_dev_attr                *d;
         struct platform_device                  *pdev;
         int ret;
 
@@ -138,6 +281,12 @@ static int __init omap1_system_dma_init(void)
                 return -ENOMEM;
         }
 
+        dma_base = ioremap(res[0].start, resource_size(&res[0]));
+        if (!dma_base) {
+                pr_err("%s: Unable to ioremap\n", __func__);
+                return -ENODEV;
+        }
+
         ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
         if (ret) {
                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
@@ -153,22 +302,84 @@ static int __init omap1_system_dma_init(void)
                 goto exit_device_put;
         }
 
+        d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
+        if (!d) {
+                dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
+                        __func__, pdev->name);
+                ret = -ENOMEM;
+                goto exit_release_p;
+        }
+
+        d->lch_count            = OMAP1_LOGICAL_DMA_CH_COUNT;
+
+        /* Valid attributes for omap1 plus processors */
+        if (cpu_is_omap15xx())
+                d->dev_caps = ENABLE_1510_MODE;
+        enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
+
+        d->dev_caps             |= SRC_PORT;
+        d->dev_caps             |= DST_PORT;
+        d->dev_caps             |= SRC_INDEX;
+        d->dev_caps             |= DST_INDEX;
+        d->dev_caps             |= IS_BURST_ONLY4;
+        d->dev_caps             |= CLEAR_CSR_ON_READ;
+        d->dev_caps             |= IS_WORD_16;
+
+
+        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
+                                        (d->lch_count), GFP_KERNEL);
+        if (!d->chan) {
+                dev_err(&pdev->dev, "%s: Memory allocation failed"
+                                        "for d->chan!!!\n", __func__);
+                goto exit_release_d;
+        }
+
+        if (cpu_is_omap15xx())
+                d->chan_count = 9;
+        else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
+                if (!(d->dev_caps & ENABLE_1510_MODE))
+                        d->chan_count = 16;
+                else
+                        d->chan_count = 9;
+        }
+
+        p->dma_attr = d;
+
+        p->show_dma_caps        = omap1_show_dma_caps;
+        p->clear_lch_regs       = omap1_clear_lch_regs;
+        p->clear_dma            = omap1_clear_dma;
+        p->dma_write            = dma_write;
+        p->dma_read             = dma_read;
+        p->disable_irq_lch      = NULL;
+
+        p->errata = configure_dma_errata();
+
         ret = platform_device_add_data(pdev, p, sizeof(*p));
         if (ret) {
                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
                         __func__, pdev->name, pdev->id);
-                goto exit_device_put;
+                goto exit_release_chan;
         }
 
         ret = platform_device_add(pdev);
         if (ret) {
                 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
                         __func__, pdev->name, pdev->id);
-                goto exit_device_put;
+                goto exit_release_chan;
         }
 
+        dma_stride              = OMAP1_DMA_STRIDE;
+        dma_common_ch_start     = CPC;
+        dma_common_ch_end       = COLOR;
+
         return ret;
 
+exit_release_chan:
+        kfree(d->chan);
+exit_release_d:
+        kfree(d);
+exit_release_p:
+        kfree(p);
 exit_device_put:
         platform_device_put(pdev);
 exit_device_del: