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authorLinus Torvalds <torvalds@g5.osdl.org>2005-11-10 13:17:11 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-11-10 13:17:11 -0500
commita46699c9a32505cb5bbfd16f76e7d4a2c84a7705 (patch)
tree5c0bc91dd1c07ab95769f5749b3b58235c758d50 /arch/arm/mach-omap1
parent7ed0175a462c4c30f6df6fac1cccac058f997739 (diff)
parentb216c01829d0b73a468204e2e763c0a818b77a46 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
Diffstat (limited to 'arch/arm/mach-omap1')
-rw-r--r--arch/arm/mach-omap1/Kconfig32
-rw-r--r--arch/arm/mach-omap1/Makefile5
-rw-r--r--arch/arm/mach-omap1/board-generic.c33
-rw-r--r--arch/arm/mach-omap1/board-h2.c15
-rw-r--r--arch/arm/mach-omap1/board-h3.c19
-rw-r--r--arch/arm/mach-omap1/board-innovator.c42
-rw-r--r--arch/arm/mach-omap1/board-netstar.c15
-rw-r--r--arch/arm/mach-omap1/board-osk.c17
-rw-r--r--arch/arm/mach-omap1/board-palmte.c87
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c23
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c9
-rw-r--r--arch/arm/mach-omap1/clock.c792
-rw-r--r--arch/arm/mach-omap1/clock.h768
-rw-r--r--arch/arm/mach-omap1/devices.c221
-rw-r--r--arch/arm/mach-omap1/id.c9
-rw-r--r--arch/arm/mach-omap1/io.c13
-rw-r--r--arch/arm/mach-omap1/irq.c23
-rw-r--r--arch/arm/mach-omap1/leds-h2p2-debug.c43
-rw-r--r--arch/arm/mach-omap1/leds.c1
-rw-r--r--arch/arm/mach-omap1/mux.c289
-rw-r--r--arch/arm/mach-omap1/serial.c9
-rw-r--r--arch/arm/mach-omap1/time.c4
22 files changed, 2155 insertions, 314 deletions
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 27fc2e8e5fca..86a0f0d14345 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -6,10 +6,10 @@ config ARCH_OMAP730
6 bool "OMAP730 Based System" 6 bool "OMAP730 Based System"
7 select ARCH_OMAP_OTG 7 select ARCH_OMAP_OTG
8 8
9config ARCH_OMAP1510 9config ARCH_OMAP15XX
10 depends on ARCH_OMAP1 10 depends on ARCH_OMAP1
11 default y 11 default y
12 bool "OMAP1510 Based System" 12 bool "OMAP15xx Based System"
13 13
14config ARCH_OMAP16XX 14config ARCH_OMAP16XX
15 depends on ARCH_OMAP1 15 depends on ARCH_OMAP1
@@ -21,7 +21,7 @@ comment "OMAP Board Type"
21 21
22config MACH_OMAP_INNOVATOR 22config MACH_OMAP_INNOVATOR
23 bool "TI Innovator" 23 bool "TI Innovator"
24 depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX) 24 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
25 help 25 help
26 TI OMAP 1510 or 1610 Innovator board support. Say Y here if you 26 TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
27 have such a board. 27 have such a board.
@@ -64,20 +64,30 @@ config MACH_OMAP_PERSEUS2
64 64
65config MACH_VOICEBLUE 65config MACH_VOICEBLUE
66 bool "Voiceblue" 66 bool "Voiceblue"
67 depends on ARCH_OMAP1 && ARCH_OMAP1510 67 depends on ARCH_OMAP1 && ARCH_OMAP15XX
68 help 68 help
69 Support for Voiceblue GSM/VoIP gateway. Say Y here if you have 69 Support for Voiceblue GSM/VoIP gateway. Say Y here if you have
70 such a board. 70 such a board.
71 71
72config MACH_NETSTAR 72config MACH_NETSTAR
73 bool "NetStar" 73 bool "NetStar"
74 depends on ARCH_OMAP1 && ARCH_OMAP1510 74 depends on ARCH_OMAP1 && ARCH_OMAP15XX
75 help 75 help
76 Support for NetStar PBX. Say Y here if you have such a board. 76 Support for NetStar PBX. Say Y here if you have such a board.
77 77
78config MACH_OMAP_PALMTE
79 bool "Palm Tungsten E"
80 depends on ARCH_OMAP1 && ARCH_OMAP15XX
81 help
82 Support for the Palm Tungsten E PDA. Currently only the LCD panel
83 is supported. To boot the kernel, you'll need a PalmOS compatible
84 bootloader; check out http://palmtelinux.sourceforge.net for more
85 informations.
86 Say Y here if you have such a PDA, say NO otherwise.
87
78config MACH_OMAP_GENERIC 88config MACH_OMAP_GENERIC
79 bool "Generic OMAP board" 89 bool "Generic OMAP board"
80 depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX) 90 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
81 help 91 help
82 Support for generic OMAP-1510, 1610 or 1710 board with 92 Support for generic OMAP-1510, 1610 or 1710 board with
83 no FPGA. Can be used as template for porting Linux to 93 no FPGA. Can be used as template for porting Linux to
@@ -121,32 +131,32 @@ config OMAP_ARM_182MHZ
121 131
122config OMAP_ARM_168MHZ 132config OMAP_ARM_168MHZ
123 bool "OMAP ARM 168 MHz CPU" 133 bool "OMAP ARM 168 MHz CPU"
124 depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730) 134 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
125 help 135 help
126 Enable 168MHz clock for OMAP CPU. If unsure, say N. 136 Enable 168MHz clock for OMAP CPU. If unsure, say N.
127 137
128config OMAP_ARM_150MHZ 138config OMAP_ARM_150MHZ
129 bool "OMAP ARM 150 MHz CPU" 139 bool "OMAP ARM 150 MHz CPU"
130 depends on ARCH_OMAP1 && ARCH_OMAP1510 140 depends on ARCH_OMAP1 && ARCH_OMAP15XX
131 help 141 help
132 Enable 150MHz clock for OMAP CPU. If unsure, say N. 142 Enable 150MHz clock for OMAP CPU. If unsure, say N.
133 143
134config OMAP_ARM_120MHZ 144config OMAP_ARM_120MHZ
135 bool "OMAP ARM 120 MHz CPU" 145 bool "OMAP ARM 120 MHz CPU"
136 depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730) 146 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
137 help 147 help
138 Enable 120MHz clock for OMAP CPU. If unsure, say N. 148 Enable 120MHz clock for OMAP CPU. If unsure, say N.
139 149
140config OMAP_ARM_60MHZ 150config OMAP_ARM_60MHZ
141 bool "OMAP ARM 60 MHz CPU" 151 bool "OMAP ARM 60 MHz CPU"
142 depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730) 152 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
143 default y 153 default y
144 help 154 help
145 Enable 60MHz clock for OMAP CPU. If unsure, say Y. 155 Enable 60MHz clock for OMAP CPU. If unsure, say Y.
146 156
147config OMAP_ARM_30MHZ 157config OMAP_ARM_30MHZ
148 bool "OMAP ARM 30 MHz CPU" 158 bool "OMAP ARM 30 MHz CPU"
149 depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730) 159 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
150 help 160 help
151 Enable 30MHz clock for OMAP CPU. If unsure, say N. 161 Enable 30MHz clock for OMAP CPU. If unsure, say N.
152 162
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 181a93deaaee..b0b00156faae 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := io.o id.o irq.o time.o serial.o devices.o 6obj-y := io.o id.o clock.o irq.o time.o mux.o serial.o devices.o
7led-y := leds.o 7led-y := leds.o
8 8
9# Specific board support 9# Specific board support
@@ -15,8 +15,9 @@ obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
15obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o 15obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o
16obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o 16obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o
17obj-$(CONFIG_MACH_NETSTAR) += board-netstar.o 17obj-$(CONFIG_MACH_NETSTAR) += board-netstar.o
18obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o
18 19
19ifeq ($(CONFIG_ARCH_OMAP1510),y) 20ifeq ($(CONFIG_ARCH_OMAP15XX),y)
20# Innovator-1510 FPGA 21# Innovator-1510 FPGA
21obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o 22obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o
22endif 23endif
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index c209c7172a9a..4b292e93fbe2 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -15,7 +15,7 @@
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/device.h> 18#include <linux/platform_device.h>
19 19
20#include <asm/hardware.h> 20#include <asm/hardware.h>
21#include <asm/mach-types.h> 21#include <asm/mach-types.h>
@@ -28,8 +28,6 @@
28#include <asm/arch/board.h> 28#include <asm/arch/board.h>
29#include <asm/arch/common.h> 29#include <asm/arch/common.h>
30 30
31static int __initdata generic_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
32
33static void __init omap_generic_init_irq(void) 31static void __init omap_generic_init_irq(void)
34{ 32{
35 omap_init_irq(); 33 omap_init_irq();
@@ -37,7 +35,7 @@ static void __init omap_generic_init_irq(void)
37 35
38/* assume no Mini-AB port */ 36/* assume no Mini-AB port */
39 37
40#ifdef CONFIG_ARCH_OMAP1510 38#ifdef CONFIG_ARCH_OMAP15XX
41static struct omap_usb_config generic1510_usb_config __initdata = { 39static struct omap_usb_config generic1510_usb_config __initdata = {
42 .register_host = 1, 40 .register_host = 1,
43 .register_dev = 1, 41 .register_dev = 1,
@@ -76,21 +74,19 @@ static struct omap_mmc_config generic_mmc_config __initdata = {
76 74
77#endif 75#endif
78 76
77static struct omap_uart_config generic_uart_config __initdata = {
78 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
79};
80
79static struct omap_board_config_kernel generic_config[] = { 81static struct omap_board_config_kernel generic_config[] = {
80 { OMAP_TAG_USB, NULL }, 82 { OMAP_TAG_USB, NULL },
81 { OMAP_TAG_MMC, &generic_mmc_config }, 83 { OMAP_TAG_MMC, &generic_mmc_config },
84 { OMAP_TAG_UART, &generic_uart_config },
82}; 85};
83 86
84static void __init omap_generic_init(void) 87static void __init omap_generic_init(void)
85{ 88{
86 const struct omap_uart_config *uart_conf; 89#ifdef CONFIG_ARCH_OMAP15XX
87
88 /*
89 * Make sure the serial ports are muxed on at this point.
90 * You have to mux them off in device drivers later on
91 * if not needed.
92 */
93#ifdef CONFIG_ARCH_OMAP1510
94 if (cpu_is_omap1510()) { 90 if (cpu_is_omap1510()) {
95 generic_config[0].data = &generic1510_usb_config; 91 generic_config[0].data = &generic1510_usb_config;
96 } 92 }
@@ -101,20 +97,9 @@ static void __init omap_generic_init(void)
101 } 97 }
102#endif 98#endif
103 99
104 uart_conf = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
105 if (uart_conf != NULL) {
106 unsigned int enabled_ports, i;
107
108 enabled_ports = uart_conf->enabled_uarts;
109 for (i = 0; i < 3; i++) {
110 if (!(enabled_ports & (1 << i)))
111 generic_serial_ports[i] = 0;
112 }
113 }
114
115 omap_board_config = generic_config; 100 omap_board_config = generic_config;
116 omap_board_config_size = ARRAY_SIZE(generic_config); 101 omap_board_config_size = ARRAY_SIZE(generic_config);
117 omap_serial_init(generic_serial_ports); 102 omap_serial_init();
118} 103}
119 104
120static void __init omap_generic_map_io(void) 105static void __init omap_generic_map_io(void)
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 4ee6bd8a50b8..a07e2c9307fa 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -40,8 +40,6 @@
40 40
41extern int omap_gpio_init(void); 41extern int omap_gpio_init(void);
42 42
43static int __initdata h2_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
44
45static struct mtd_partition h2_partitions[] = { 43static struct mtd_partition h2_partitions[] = {
46 /* bootloader (U-Boot, etc) in first sector */ 44 /* bootloader (U-Boot, etc) in first sector */
47 { 45 {
@@ -160,9 +158,20 @@ static struct omap_mmc_config h2_mmc_config __initdata = {
160 }, 158 },
161}; 159};
162 160
161static struct omap_uart_config h2_uart_config __initdata = {
162 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
163};
164
165static struct omap_lcd_config h2_lcd_config __initdata = {
166 .panel_name = "h2",
167 .ctrl_name = "internal",
168};
169
163static struct omap_board_config_kernel h2_config[] = { 170static struct omap_board_config_kernel h2_config[] = {
164 { OMAP_TAG_USB, &h2_usb_config }, 171 { OMAP_TAG_USB, &h2_usb_config },
165 { OMAP_TAG_MMC, &h2_mmc_config }, 172 { OMAP_TAG_MMC, &h2_mmc_config },
173 { OMAP_TAG_UART, &h2_uart_config },
174 { OMAP_TAG_LCD, &h2_lcd_config },
166}; 175};
167 176
168static void __init h2_init(void) 177static void __init h2_init(void)
@@ -180,12 +189,12 @@ static void __init h2_init(void)
180 platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); 189 platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
181 omap_board_config = h2_config; 190 omap_board_config = h2_config;
182 omap_board_config_size = ARRAY_SIZE(h2_config); 191 omap_board_config_size = ARRAY_SIZE(h2_config);
192 omap_serial_init();
183} 193}
184 194
185static void __init h2_map_io(void) 195static void __init h2_map_io(void)
186{ 196{
187 omap_map_common_io(); 197 omap_map_common_io();
188 omap_serial_init(h2_serial_ports);
189} 198}
190 199
191MACHINE_START(OMAP_H2, "TI-H2") 200MACHINE_START(OMAP_H2, "TI-H2")
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index fc824361430d..668e278433c2 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -41,8 +41,6 @@
41 41
42extern int omap_gpio_init(void); 42extern int omap_gpio_init(void);
43 43
44static int __initdata h3_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
45
46static struct mtd_partition h3_partitions[] = { 44static struct mtd_partition h3_partitions[] = {
47 /* bootloader (U-Boot, etc) in first sector */ 45 /* bootloader (U-Boot, etc) in first sector */
48 { 46 {
@@ -168,9 +166,20 @@ static struct omap_mmc_config h3_mmc_config __initdata = {
168 }, 166 },
169}; 167};
170 168
169static struct omap_uart_config h3_uart_config __initdata = {
170 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
171};
172
173static struct omap_lcd_config h3_lcd_config __initdata = {
174 .panel_name = "h3",
175 .ctrl_name = "internal",
176};
177
171static struct omap_board_config_kernel h3_config[] = { 178static struct omap_board_config_kernel h3_config[] = {
172 { OMAP_TAG_USB, &h3_usb_config }, 179 { OMAP_TAG_USB, &h3_usb_config },
173 { OMAP_TAG_MMC, &h3_mmc_config }, 180 { OMAP_TAG_MMC, &h3_mmc_config },
181 { OMAP_TAG_UART, &h3_uart_config },
182 { OMAP_TAG_LCD, &h3_lcd_config },
174}; 183};
175 184
176static void __init h3_init(void) 185static void __init h3_init(void)
@@ -180,6 +189,7 @@ static void __init h3_init(void)
180 (void) platform_add_devices(devices, ARRAY_SIZE(devices)); 189 (void) platform_add_devices(devices, ARRAY_SIZE(devices));
181 omap_board_config = h3_config; 190 omap_board_config = h3_config;
182 omap_board_config_size = ARRAY_SIZE(h3_config); 191 omap_board_config_size = ARRAY_SIZE(h3_config);
192 omap_serial_init();
183} 193}
184 194
185static void __init h3_init_smc91x(void) 195static void __init h3_init_smc91x(void)
@@ -201,7 +211,6 @@ void h3_init_irq(void)
201static void __init h3_map_io(void) 211static void __init h3_map_io(void)
202{ 212{
203 omap_map_common_io(); 213 omap_map_common_io();
204 omap_serial_init(h3_serial_ports);
205} 214}
206 215
207MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") 216MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index a2eac853b2da..95f1ff36cdcb 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -36,8 +36,6 @@
36#include <asm/arch/usb.h> 36#include <asm/arch/usb.h>
37#include <asm/arch/common.h> 37#include <asm/arch/common.h>
38 38
39static int __initdata innovator_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
40
41static struct mtd_partition innovator_partitions[] = { 39static struct mtd_partition innovator_partitions[] = {
42 /* bootloader (U-Boot, etc) in first sector */ 40 /* bootloader (U-Boot, etc) in first sector */
43 { 41 {
@@ -99,7 +97,7 @@ static struct platform_device innovator_flash_device = {
99 .resource = &innovator_flash_resource, 97 .resource = &innovator_flash_resource,
100}; 98};
101 99
102#ifdef CONFIG_ARCH_OMAP1510 100#ifdef CONFIG_ARCH_OMAP15XX
103 101
104/* Only FPGA needs to be mapped here. All others are done with ioremap */ 102/* Only FPGA needs to be mapped here. All others are done with ioremap */
105static struct map_desc innovator1510_io_desc[] __initdata = { 103static struct map_desc innovator1510_io_desc[] __initdata = {
@@ -136,7 +134,7 @@ static struct platform_device *innovator1510_devices[] __initdata = {
136 &innovator1510_smc91x_device, 134 &innovator1510_smc91x_device,
137}; 135};
138 136
139#endif /* CONFIG_ARCH_OMAP1510 */ 137#endif /* CONFIG_ARCH_OMAP15XX */
140 138
141#ifdef CONFIG_ARCH_OMAP16XX 139#ifdef CONFIG_ARCH_OMAP16XX
142 140
@@ -185,7 +183,7 @@ void innovator_init_irq(void)
185{ 183{
186 omap_init_irq(); 184 omap_init_irq();
187 omap_gpio_init(); 185 omap_gpio_init();
188#ifdef CONFIG_ARCH_OMAP1510 186#ifdef CONFIG_ARCH_OMAP15XX
189 if (cpu_is_omap1510()) { 187 if (cpu_is_omap1510()) {
190 omap1510_fpga_init_irq(); 188 omap1510_fpga_init_irq();
191 } 189 }
@@ -193,7 +191,7 @@ void innovator_init_irq(void)
193 innovator_init_smc91x(); 191 innovator_init_smc91x();
194} 192}
195 193
196#ifdef CONFIG_ARCH_OMAP1510 194#ifdef CONFIG_ARCH_OMAP15XX
197static struct omap_usb_config innovator1510_usb_config __initdata = { 195static struct omap_usb_config innovator1510_usb_config __initdata = {
198 /* for bundled non-standard host and peripheral cables */ 196 /* for bundled non-standard host and peripheral cables */
199 .hmc_mode = 4, 197 .hmc_mode = 4,
@@ -205,6 +203,11 @@ static struct omap_usb_config innovator1510_usb_config __initdata = {
205 .register_dev = 1, 203 .register_dev = 1,
206 .pins[0] = 2, 204 .pins[0] = 2,
207}; 205};
206
207static struct omap_lcd_config innovator1510_lcd_config __initdata = {
208 .panel_name = "inn1510",
209 .ctrl_name = "internal",
210};
208#endif 211#endif
209 212
210#ifdef CONFIG_ARCH_OMAP16XX 213#ifdef CONFIG_ARCH_OMAP16XX
@@ -222,6 +225,11 @@ static struct omap_usb_config h2_usb_config __initdata = {
222 225
223 .pins[1] = 3, 226 .pins[1] = 3,
224}; 227};
228
229static struct omap_lcd_config innovator1610_lcd_config __initdata = {
230 .panel_name = "inn1610",
231 .ctrl_name = "internal",
232};
225#endif 233#endif
226 234
227static struct omap_mmc_config innovator_mmc_config __initdata = { 235static struct omap_mmc_config innovator_mmc_config __initdata = {
@@ -234,14 +242,20 @@ static struct omap_mmc_config innovator_mmc_config __initdata = {
234 }, 242 },
235}; 243};
236 244
245static struct omap_uart_config innovator_uart_config __initdata = {
246 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
247};
248
237static struct omap_board_config_kernel innovator_config[] = { 249static struct omap_board_config_kernel innovator_config[] = {
238 { OMAP_TAG_USB, NULL }, 250 { OMAP_TAG_USB, NULL },
251 { OMAP_TAG_LCD, NULL },
239 { OMAP_TAG_MMC, &innovator_mmc_config }, 252 { OMAP_TAG_MMC, &innovator_mmc_config },
253 { OMAP_TAG_UART, &innovator_uart_config },
240}; 254};
241 255
242static void __init innovator_init(void) 256static void __init innovator_init(void)
243{ 257{
244#ifdef CONFIG_ARCH_OMAP1510 258#ifdef CONFIG_ARCH_OMAP15XX
245 if (cpu_is_omap1510()) { 259 if (cpu_is_omap1510()) {
246 platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices)); 260 platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices));
247 } 261 }
@@ -252,23 +266,28 @@ static void __init innovator_init(void)
252 } 266 }
253#endif 267#endif
254 268
255#ifdef CONFIG_ARCH_OMAP1510 269#ifdef CONFIG_ARCH_OMAP15XX
256 if (cpu_is_omap1510()) 270 if (cpu_is_omap1510()) {
257 innovator_config[0].data = &innovator1510_usb_config; 271 innovator_config[0].data = &innovator1510_usb_config;
272 innovator_config[1].data = &innovator1510_lcd_config;
273 }
258#endif 274#endif
259#ifdef CONFIG_ARCH_OMAP16XX 275#ifdef CONFIG_ARCH_OMAP16XX
260 if (cpu_is_omap1610()) 276 if (cpu_is_omap1610()) {
261 innovator_config[0].data = &h2_usb_config; 277 innovator_config[0].data = &h2_usb_config;
278 innovator_config[1].data = &innovator1610_lcd_config;
279 }
262#endif 280#endif
263 omap_board_config = innovator_config; 281 omap_board_config = innovator_config;
264 omap_board_config_size = ARRAY_SIZE(innovator_config); 282 omap_board_config_size = ARRAY_SIZE(innovator_config);
283 omap_serial_init();
265} 284}
266 285
267static void __init innovator_map_io(void) 286static void __init innovator_map_io(void)
268{ 287{
269 omap_map_common_io(); 288 omap_map_common_io();
270 289
271#ifdef CONFIG_ARCH_OMAP1510 290#ifdef CONFIG_ARCH_OMAP15XX
272 if (cpu_is_omap1510()) { 291 if (cpu_is_omap1510()) {
273 iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc)); 292 iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
274 udelay(10); /* Delay needed for FPGA */ 293 udelay(10); /* Delay needed for FPGA */
@@ -280,7 +299,6 @@ static void __init innovator_map_io(void)
280 fpga_read(OMAP1510_FPGA_BOARD_REV)); 299 fpga_read(OMAP1510_FPGA_BOARD_REV));
281 } 300 }
282#endif 301#endif
283 omap_serial_init(innovator_serial_ports);
284} 302}
285 303
286MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") 304MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
diff --git a/arch/arm/mach-omap1/board-netstar.c b/arch/arm/mach-omap1/board-netstar.c
index c851c2e4dfcb..0448fa7de8a4 100644
--- a/arch/arm/mach-omap1/board-netstar.c
+++ b/arch/arm/mach-omap1/board-netstar.c
@@ -55,6 +55,14 @@ static struct platform_device *netstar_devices[] __initdata = {
55 &netstar_smc91x_device, 55 &netstar_smc91x_device,
56}; 56};
57 57
58static struct omap_uart_config netstar_uart_config __initdata = {
59 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
60};
61
62static struct omap_board_config_kernel netstar_config[] = {
63 { OMAP_TAG_UART, &netstar_uart_config },
64};
65
58static void __init netstar_init_irq(void) 66static void __init netstar_init_irq(void)
59{ 67{
60 omap_init_irq(); 68 omap_init_irq();
@@ -92,14 +100,15 @@ static void __init netstar_init(void)
92 /* Switch off red LED */ 100 /* Switch off red LED */
93 omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ 101 omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
94 omap_writeb(0x80, OMAP_LPG1_LCR); 102 omap_writeb(0x80, OMAP_LPG1_LCR);
95}
96 103
97static int __initdata omap_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1}; 104 omap_board_config = netstar_config;
105 omap_board_config_size = ARRAY_SIZE(netstar_config);
106 omap_serial_init();
107}
98 108
99static void __init netstar_map_io(void) 109static void __init netstar_map_io(void)
100{ 110{
101 omap_map_common_io(); 111 omap_map_common_io();
102 omap_serial_init(omap_serial_ports);
103} 112}
104 113
105#define MACHINE_PANICED 1 114#define MACHINE_PANICED 1
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index a88524e7c315..e990e1bc1669 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -46,8 +46,6 @@
46#include <asm/arch/tc.h> 46#include <asm/arch/tc.h>
47#include <asm/arch/common.h> 47#include <asm/arch/common.h>
48 48
49static int __initdata osk_serial_ports[OMAP_MAX_NR_PORTS] = {1, 0, 0};
50
51static struct mtd_partition osk_partitions[] = { 49static struct mtd_partition osk_partitions[] = {
52 /* bootloader (U-Boot, etc) in first sector */ 50 /* bootloader (U-Boot, etc) in first sector */
53 { 51 {
@@ -155,7 +153,7 @@ static void __init osk_init_smc91x(void)
155 } 153 }
156 154
157 /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */ 155 /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */
158 EMIFS_CCS(1) |= 0x2; 156 EMIFS_CCS(1) |= 0x3;
159} 157}
160 158
161static void __init osk_init_cf(void) 159static void __init osk_init_cf(void)
@@ -193,8 +191,19 @@ static struct omap_usb_config osk_usb_config __initdata = {
193 .pins[0] = 2, 191 .pins[0] = 2,
194}; 192};
195 193
194static struct omap_uart_config osk_uart_config __initdata = {
195 .enabled_uarts = (1 << 0),
196};
197
198static struct omap_lcd_config osk_lcd_config __initdata = {
199 .panel_name = "osk",
200 .ctrl_name = "internal",
201};
202
196static struct omap_board_config_kernel osk_config[] = { 203static struct omap_board_config_kernel osk_config[] = {
197 { OMAP_TAG_USB, &osk_usb_config }, 204 { OMAP_TAG_USB, &osk_usb_config },
205 { OMAP_TAG_UART, &osk_uart_config },
206 { OMAP_TAG_LCD, &osk_lcd_config },
198}; 207};
199 208
200#ifdef CONFIG_OMAP_OSK_MISTRAL 209#ifdef CONFIG_OMAP_OSK_MISTRAL
@@ -254,13 +263,13 @@ static void __init osk_init(void)
254 omap_board_config_size = ARRAY_SIZE(osk_config); 263 omap_board_config_size = ARRAY_SIZE(osk_config);
255 USB_TRANSCEIVER_CTRL_REG |= (3 << 1); 264 USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
256 265
266 omap_serial_init();
257 osk_mistral_init(); 267 osk_mistral_init();
258} 268}
259 269
260static void __init osk_map_io(void) 270static void __init osk_map_io(void)
261{ 271{
262 omap_map_common_io(); 272 omap_map_common_io();
263 omap_serial_init(osk_serial_ports);
264} 273}
265 274
266MACHINE_START(OMAP_OSK, "TI-OSK") 275MACHINE_START(OMAP_OSK, "TI-OSK")
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
new file mode 100644
index 000000000000..540b20d78cca
--- /dev/null
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -0,0 +1,87 @@
1/*
2 * linux/arch/arm/mach-omap1/board-palmte.c
3 *
4 * Modified from board-generic.c
5 *
6 * Support for the Palm Tungsten E PDA.
7 *
8 * Original version : Laurent Gonzalez
9 *
10 * Maintainters : http://palmtelinux.sf.net
11 * palmtelinux-developpers@lists.sf.net
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/notifier.h>
22
23#include <asm/hardware.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27
28#include <asm/arch/gpio.h>
29#include <asm/arch/mux.h>
30#include <asm/arch/usb.h>
31#include <asm/arch/board.h>
32#include <asm/arch/common.h>
33#include <asm/hardware/clock.h>
34
35static void __init omap_generic_init_irq(void)
36{
37 omap_init_irq();
38}
39
40static struct omap_usb_config palmte_usb_config __initdata = {
41 .register_dev = 1,
42 .hmc_mode = 0,
43 .pins[0] = 3,
44};
45
46static struct omap_mmc_config palmte_mmc_config __initdata = {
47 .mmc [0] = {
48 .enabled = 1,
49 .wire4 = 1,
50 .wp_pin = OMAP_MPUIO(3),
51 .power_pin = -1,
52 .switch_pin = -1,
53 },
54};
55
56static struct omap_lcd_config palmte_lcd_config __initdata = {
57 .panel_name = "palmte",
58 .ctrl_name = "internal",
59};
60
61static struct omap_board_config_kernel palmte_config[] = {
62 { OMAP_TAG_USB, &palmte_usb_config },
63 { OMAP_TAG_MMC, &palmte_mmc_config },
64 { OMAP_TAG_LCD, &palmte_lcd_config },
65};
66
67static void __init omap_generic_init(void)
68{
69 omap_board_config = palmte_config;
70 omap_board_config_size = ARRAY_SIZE(palmte_config);
71}
72
73static void __init omap_generic_map_io(void)
74{
75 omap_map_common_io();
76}
77
78MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
79 .phys_ram = 0x10000000,
80 .phys_io = 0xfff00000,
81 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
82 .boot_params = 0x10000100,
83 .map_io = omap_generic_map_io,
84 .init_irq = omap_generic_init_irq,
85 .init_machine = omap_generic_init,
86 .timer = &omap_timer,
87MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 354b157acb3a..bd900b7ab33c 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -29,6 +29,7 @@
29#include <asm/arch/mux.h> 29#include <asm/arch/mux.h>
30#include <asm/arch/fpga.h> 30#include <asm/arch/fpga.h>
31#include <asm/arch/common.h> 31#include <asm/arch/common.h>
32#include <asm/arch/board.h>
32 33
33static struct resource smc91x_resources[] = { 34static struct resource smc91x_resources[] = {
34 [0] = { 35 [0] = {
@@ -43,8 +44,6 @@ static struct resource smc91x_resources[] = {
43 }, 44 },
44}; 45};
45 46
46static int __initdata p2_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 0};
47
48static struct mtd_partition p2_partitions[] = { 47static struct mtd_partition p2_partitions[] = {
49 /* bootloader (U-Boot, etc) in first sector */ 48 /* bootloader (U-Boot, etc) in first sector */
50 { 49 {
@@ -111,9 +110,27 @@ static struct platform_device *devices[] __initdata = {
111 &smc91x_device, 110 &smc91x_device,
112}; 111};
113 112
113static struct omap_uart_config perseus2_uart_config __initdata = {
114 .enabled_uarts = ((1 << 0) | (1 << 1)),
115};
116
117static struct omap_lcd_config perseus2_lcd_config __initdata = {
118 .panel_name = "p2",
119 .ctrl_name = "internal",
120};
121
122static struct omap_board_config_kernel perseus2_config[] = {
123 { OMAP_TAG_UART, &perseus2_uart_config },
124 { OMAP_TAG_LCD, &perseus2_lcd_config },
125};
126
114static void __init omap_perseus2_init(void) 127static void __init omap_perseus2_init(void)
115{ 128{
116 (void) platform_add_devices(devices, ARRAY_SIZE(devices)); 129 (void) platform_add_devices(devices, ARRAY_SIZE(devices));
130
131 omap_board_config = perseus2_config;
132 omap_board_config_size = ARRAY_SIZE(perseus2_config);
133 omap_serial_init();
117} 134}
118 135
119static void __init perseus2_init_smc91x(void) 136static void __init perseus2_init_smc91x(void)
@@ -131,7 +148,6 @@ void omap_perseus2_init_irq(void)
131 omap_gpio_init(); 148 omap_gpio_init();
132 perseus2_init_smc91x(); 149 perseus2_init_smc91x();
133} 150}
134
135/* Only FPGA needs to be mapped here. All others are done with ioremap */ 151/* Only FPGA needs to be mapped here. All others are done with ioremap */
136static struct map_desc omap_perseus2_io_desc[] __initdata = { 152static struct map_desc omap_perseus2_io_desc[] __initdata = {
137 { 153 {
@@ -179,7 +195,6 @@ static void __init omap_perseus2_map_io(void)
179 * It is used as the Ethernet controller interrupt 195 * It is used as the Ethernet controller interrupt
180 */ 196 */
181 omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9); 197 omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
182 omap_serial_init(p2_serial_ports);
183} 198}
184 199
185MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") 200MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 3f018b296861..6f9a6220e78a 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -150,9 +150,14 @@ static struct omap_mmc_config voiceblue_mmc_config __initdata = {
150 }, 150 },
151}; 151};
152 152
153static struct omap_uart_config voiceblue_uart_config __initdata = {
154 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
155};
156
153static struct omap_board_config_kernel voiceblue_config[] = { 157static struct omap_board_config_kernel voiceblue_config[] = {
154 { OMAP_TAG_USB, &voiceblue_usb_config }, 158 { OMAP_TAG_USB, &voiceblue_usb_config },
155 { OMAP_TAG_MMC, &voiceblue_mmc_config }, 159 { OMAP_TAG_MMC, &voiceblue_mmc_config },
160 { OMAP_TAG_UART, &voiceblue_uart_config },
156}; 161};
157 162
158static void __init voiceblue_init_irq(void) 163static void __init voiceblue_init_irq(void)
@@ -191,6 +196,7 @@ static void __init voiceblue_init(void)
191 platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); 196 platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
192 omap_board_config = voiceblue_config; 197 omap_board_config = voiceblue_config;
193 omap_board_config_size = ARRAY_SIZE(voiceblue_config); 198 omap_board_config_size = ARRAY_SIZE(voiceblue_config);
199 omap_serial_init();
194 200
195 /* There is a good chance board is going up, so enable power LED 201 /* There is a good chance board is going up, so enable power LED
196 * (it is connected through invertor) */ 202 * (it is connected through invertor) */
@@ -198,12 +204,9 @@ static void __init voiceblue_init(void)
198 omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ 204 omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
199} 205}
200 206
201static int __initdata omap_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
202
203static void __init voiceblue_map_io(void) 207static void __init voiceblue_map_io(void)
204{ 208{
205 omap_map_common_io(); 209 omap_map_common_io();
206 omap_serial_init(omap_serial_ports);
207} 210}
208 211
209#define MACHINE_PANICED 1 212#define MACHINE_PANICED 1
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
new file mode 100644
index 000000000000..4277eee44ed5
--- /dev/null
+++ b/arch/arm/mach-omap1/clock.c
@@ -0,0 +1,792 @@
1/*
2 * linux/arch/arm/mach-omap1/clock.c
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 *
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19
20#include <asm/io.h>
21#include <asm/hardware/clock.h>
22
23#include <asm/arch/usb.h>
24#include <asm/arch/clock.h>
25#include <asm/arch/sram.h>
26
27#include "clock.h"
28
29__u32 arm_idlect1_mask;
30
31/*-------------------------------------------------------------------------
32 * Omap1 specific clock functions
33 *-------------------------------------------------------------------------*/
34
35static void omap1_watchdog_recalc(struct clk * clk)
36{
37 clk->rate = clk->parent->rate / 14;
38}
39
40static void omap1_uart_recalc(struct clk * clk)
41{
42 unsigned int val = omap_readl(clk->enable_reg);
43 if (val & clk->enable_bit)
44 clk->rate = 48000000;
45 else
46 clk->rate = 12000000;
47}
48
49static int omap1_clk_enable_dsp_domain(struct clk *clk)
50{
51 int retval;
52
53 retval = omap1_clk_use(&api_ck.clk);
54 if (!retval) {
55 retval = omap1_clk_enable(clk);
56 omap1_clk_unuse(&api_ck.clk);
57 }
58
59 return retval;
60}
61
62static void omap1_clk_disable_dsp_domain(struct clk *clk)
63{
64 if (omap1_clk_use(&api_ck.clk) == 0) {
65 omap1_clk_disable(clk);
66 omap1_clk_unuse(&api_ck.clk);
67 }
68}
69
70static int omap1_clk_enable_uart_functional(struct clk *clk)
71{
72 int ret;
73 struct uart_clk *uclk;
74
75 ret = omap1_clk_enable(clk);
76 if (ret == 0) {
77 /* Set smart idle acknowledgement mode */
78 uclk = (struct uart_clk *)clk;
79 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
80 uclk->sysc_addr);
81 }
82
83 return ret;
84}
85
86static void omap1_clk_disable_uart_functional(struct clk *clk)
87{
88 struct uart_clk *uclk;
89
90 /* Set force idle acknowledgement mode */
91 uclk = (struct uart_clk *)clk;
92 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
93
94 omap1_clk_disable(clk);
95}
96
97static void omap1_clk_allow_idle(struct clk *clk)
98{
99 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
100
101 if (!(clk->flags & CLOCK_IDLE_CONTROL))
102 return;
103
104 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
105 arm_idlect1_mask |= 1 << iclk->idlect_shift;
106}
107
108static void omap1_clk_deny_idle(struct clk *clk)
109{
110 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
111
112 if (!(clk->flags & CLOCK_IDLE_CONTROL))
113 return;
114
115 if (iclk->no_idle_count++ == 0)
116 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
117}
118
119static __u16 verify_ckctl_value(__u16 newval)
120{
121 /* This function checks for following limitations set
122 * by the hardware (all conditions must be true):
123 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
124 * ARM_CK >= TC_CK
125 * DSP_CK >= TC_CK
126 * DSPMMU_CK >= TC_CK
127 *
128 * In addition following rules are enforced:
129 * LCD_CK <= TC_CK
130 * ARMPER_CK <= TC_CK
131 *
132 * However, maximum frequencies are not checked for!
133 */
134 __u8 per_exp;
135 __u8 lcd_exp;
136 __u8 arm_exp;
137 __u8 dsp_exp;
138 __u8 tc_exp;
139 __u8 dspmmu_exp;
140
141 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
142 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
143 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
144 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
145 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
146 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
147
148 if (dspmmu_exp < dsp_exp)
149 dspmmu_exp = dsp_exp;
150 if (dspmmu_exp > dsp_exp+1)
151 dspmmu_exp = dsp_exp+1;
152 if (tc_exp < arm_exp)
153 tc_exp = arm_exp;
154 if (tc_exp < dspmmu_exp)
155 tc_exp = dspmmu_exp;
156 if (tc_exp > lcd_exp)
157 lcd_exp = tc_exp;
158 if (tc_exp > per_exp)
159 per_exp = tc_exp;
160
161 newval &= 0xf000;
162 newval |= per_exp << CKCTL_PERDIV_OFFSET;
163 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
164 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
165 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
166 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
167 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
168
169 return newval;
170}
171
172static int calc_dsor_exp(struct clk *clk, unsigned long rate)
173{
174 /* Note: If target frequency is too low, this function will return 4,
175 * which is invalid value. Caller must check for this value and act
176 * accordingly.
177 *
178 * Note: This function does not check for following limitations set
179 * by the hardware (all conditions must be true):
180 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
181 * ARM_CK >= TC_CK
182 * DSP_CK >= TC_CK
183 * DSPMMU_CK >= TC_CK
184 */
185 unsigned long realrate;
186 struct clk * parent;
187 unsigned dsor_exp;
188
189 if (unlikely(!(clk->flags & RATE_CKCTL)))
190 return -EINVAL;
191
192 parent = clk->parent;
193 if (unlikely(parent == 0))
194 return -EIO;
195
196 realrate = parent->rate;
197 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
198 if (realrate <= rate)
199 break;
200
201 realrate /= 2;
202 }
203
204 return dsor_exp;
205}
206
207static void omap1_ckctl_recalc(struct clk * clk)
208{
209 int dsor;
210
211 /* Calculate divisor encoded as 2-bit exponent */
212 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
213
214 if (unlikely(clk->rate == clk->parent->rate / dsor))
215 return; /* No change, quick exit */
216 clk->rate = clk->parent->rate / dsor;
217
218 if (unlikely(clk->flags & RATE_PROPAGATES))
219 propagate_rate(clk);
220}
221
222static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
223{
224 int dsor;
225
226 /* Calculate divisor encoded as 2-bit exponent
227 *
228 * The clock control bits are in DSP domain,
229 * so api_ck is needed for access.
230 * Note that DSP_CKCTL virt addr = phys addr, so
231 * we must use __raw_readw() instead of omap_readw().
232 */
233 omap1_clk_use(&api_ck.clk);
234 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
235 omap1_clk_unuse(&api_ck.clk);
236
237 if (unlikely(clk->rate == clk->parent->rate / dsor))
238 return; /* No change, quick exit */
239 clk->rate = clk->parent->rate / dsor;
240
241 if (unlikely(clk->flags & RATE_PROPAGATES))
242 propagate_rate(clk);
243}
244
245/* MPU virtual clock functions */
246static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
247{
248 /* Find the highest supported frequency <= rate and switch to it */
249 struct mpu_rate * ptr;
250
251 if (clk != &virtual_ck_mpu)
252 return -EINVAL;
253
254 for (ptr = rate_table; ptr->rate; ptr++) {
255 if (ptr->xtal != ck_ref.rate)
256 continue;
257
258 /* DPLL1 cannot be reprogrammed without risking system crash */
259 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
260 continue;
261
262 /* Can check only after xtal frequency check */
263 if (ptr->rate <= rate)
264 break;
265 }
266
267 if (!ptr->rate)
268 return -EINVAL;
269
270 /*
271 * In most cases we should not need to reprogram DPLL.
272 * Reprogramming the DPLL is tricky, it must be done from SRAM.
273 */
274 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
275
276 ck_dpll1.rate = ptr->pll_rate;
277 propagate_rate(&ck_dpll1);
278 return 0;
279}
280
281static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
282{
283 int ret = -EINVAL;
284 int dsor_exp;
285 __u16 regval;
286
287 if (clk->flags & RATE_CKCTL) {
288 dsor_exp = calc_dsor_exp(clk, rate);
289 if (dsor_exp > 3)
290 dsor_exp = -EINVAL;
291 if (dsor_exp < 0)
292 return dsor_exp;
293
294 regval = __raw_readw(DSP_CKCTL);
295 regval &= ~(3 << clk->rate_offset);
296 regval |= dsor_exp << clk->rate_offset;
297 __raw_writew(regval, DSP_CKCTL);
298 clk->rate = clk->parent->rate / (1 << dsor_exp);
299 ret = 0;
300 }
301
302 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
303 propagate_rate(clk);
304
305 return ret;
306}
307
308static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
309{
310 /* Find the highest supported frequency <= rate */
311 struct mpu_rate * ptr;
312 long highest_rate;
313
314 if (clk != &virtual_ck_mpu)
315 return -EINVAL;
316
317 highest_rate = -EINVAL;
318
319 for (ptr = rate_table; ptr->rate; ptr++) {
320 if (ptr->xtal != ck_ref.rate)
321 continue;
322
323 highest_rate = ptr->rate;
324
325 /* Can check only after xtal frequency check */
326 if (ptr->rate <= rate)
327 break;
328 }
329
330 return highest_rate;
331}
332
333static unsigned calc_ext_dsor(unsigned long rate)
334{
335 unsigned dsor;
336
337 /* MCLK and BCLK divisor selection is not linear:
338 * freq = 96MHz / dsor
339 *
340 * RATIO_SEL range: dsor <-> RATIO_SEL
341 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
342 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
343 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
344 * can not be used.
345 */
346 for (dsor = 2; dsor < 96; ++dsor) {
347 if ((dsor & 1) && dsor > 8)
348 continue;
349 if (rate >= 96000000 / dsor)
350 break;
351 }
352 return dsor;
353}
354
355/* Only needed on 1510 */
356static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
357{
358 unsigned int val;
359
360 val = omap_readl(clk->enable_reg);
361 if (rate == 12000000)
362 val &= ~(1 << clk->enable_bit);
363 else if (rate == 48000000)
364 val |= (1 << clk->enable_bit);
365 else
366 return -EINVAL;
367 omap_writel(val, clk->enable_reg);
368 clk->rate = rate;
369
370 return 0;
371}
372
373/* External clock (MCLK & BCLK) functions */
374static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
375{
376 unsigned dsor;
377 __u16 ratio_bits;
378
379 dsor = calc_ext_dsor(rate);
380 clk->rate = 96000000 / dsor;
381 if (dsor > 8)
382 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
383 else
384 ratio_bits = (dsor - 2) << 2;
385
386 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
387 omap_writew(ratio_bits, clk->enable_reg);
388
389 return 0;
390}
391
392static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
393{
394 return 96000000 / calc_ext_dsor(rate);
395}
396
397static void omap1_init_ext_clk(struct clk * clk)
398{
399 unsigned dsor;
400 __u16 ratio_bits;
401
402 /* Determine current rate and ensure clock is based on 96MHz APLL */
403 ratio_bits = omap_readw(clk->enable_reg) & ~1;
404 omap_writew(ratio_bits, clk->enable_reg);
405
406 ratio_bits = (ratio_bits & 0xfc) >> 2;
407 if (ratio_bits > 6)
408 dsor = (ratio_bits - 6) * 2 + 8;
409 else
410 dsor = ratio_bits + 2;
411
412 clk-> rate = 96000000 / dsor;
413}
414
415static int omap1_clk_use(struct clk *clk)
416{
417 int ret = 0;
418 if (clk->usecount++ == 0) {
419 if (likely(clk->parent)) {
420 ret = omap1_clk_use(clk->parent);
421
422 if (unlikely(ret != 0)) {
423 clk->usecount--;
424 return ret;
425 }
426
427 if (clk->flags & CLOCK_NO_IDLE_PARENT)
428 if (!cpu_is_omap24xx())
429 omap1_clk_deny_idle(clk->parent);
430 }
431
432 ret = clk->enable(clk);
433
434 if (unlikely(ret != 0) && clk->parent) {
435 omap1_clk_unuse(clk->parent);
436 clk->usecount--;
437 }
438 }
439
440 return ret;
441}
442
443static void omap1_clk_unuse(struct clk *clk)
444{
445 if (clk->usecount > 0 && !(--clk->usecount)) {
446 clk->disable(clk);
447 if (likely(clk->parent)) {
448 omap1_clk_unuse(clk->parent);
449 if (clk->flags & CLOCK_NO_IDLE_PARENT)
450 if (!cpu_is_omap24xx())
451 omap1_clk_allow_idle(clk->parent);
452 }
453 }
454}
455
456static int omap1_clk_enable(struct clk *clk)
457{
458 __u16 regval16;
459 __u32 regval32;
460
461 if (clk->flags & ALWAYS_ENABLED)
462 return 0;
463
464 if (unlikely(clk->enable_reg == 0)) {
465 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
466 clk->name);
467 return 0;
468 }
469
470 if (clk->flags & ENABLE_REG_32BIT) {
471 if (clk->flags & VIRTUAL_IO_ADDRESS) {
472 regval32 = __raw_readl(clk->enable_reg);
473 regval32 |= (1 << clk->enable_bit);
474 __raw_writel(regval32, clk->enable_reg);
475 } else {
476 regval32 = omap_readl(clk->enable_reg);
477 regval32 |= (1 << clk->enable_bit);
478 omap_writel(regval32, clk->enable_reg);
479 }
480 } else {
481 if (clk->flags & VIRTUAL_IO_ADDRESS) {
482 regval16 = __raw_readw(clk->enable_reg);
483 regval16 |= (1 << clk->enable_bit);
484 __raw_writew(regval16, clk->enable_reg);
485 } else {
486 regval16 = omap_readw(clk->enable_reg);
487 regval16 |= (1 << clk->enable_bit);
488 omap_writew(regval16, clk->enable_reg);
489 }
490 }
491
492 return 0;
493}
494
495static void omap1_clk_disable(struct clk *clk)
496{
497 __u16 regval16;
498 __u32 regval32;
499
500 if (clk->enable_reg == 0)
501 return;
502
503 if (clk->flags & ENABLE_REG_32BIT) {
504 if (clk->flags & VIRTUAL_IO_ADDRESS) {
505 regval32 = __raw_readl(clk->enable_reg);
506 regval32 &= ~(1 << clk->enable_bit);
507 __raw_writel(regval32, clk->enable_reg);
508 } else {
509 regval32 = omap_readl(clk->enable_reg);
510 regval32 &= ~(1 << clk->enable_bit);
511 omap_writel(regval32, clk->enable_reg);
512 }
513 } else {
514 if (clk->flags & VIRTUAL_IO_ADDRESS) {
515 regval16 = __raw_readw(clk->enable_reg);
516 regval16 &= ~(1 << clk->enable_bit);
517 __raw_writew(regval16, clk->enable_reg);
518 } else {
519 regval16 = omap_readw(clk->enable_reg);
520 regval16 &= ~(1 << clk->enable_bit);
521 omap_writew(regval16, clk->enable_reg);
522 }
523 }
524}
525
526static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
527{
528 int dsor_exp;
529
530 if (clk->flags & RATE_FIXED)
531 return clk->rate;
532
533 if (clk->flags & RATE_CKCTL) {
534 dsor_exp = calc_dsor_exp(clk, rate);
535 if (dsor_exp < 0)
536 return dsor_exp;
537 if (dsor_exp > 3)
538 dsor_exp = 3;
539 return clk->parent->rate / (1 << dsor_exp);
540 }
541
542 if(clk->round_rate != 0)
543 return clk->round_rate(clk, rate);
544
545 return clk->rate;
546}
547
548static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
549{
550 int ret = -EINVAL;
551 int dsor_exp;
552 __u16 regval;
553
554 if (clk->set_rate)
555 ret = clk->set_rate(clk, rate);
556 else if (clk->flags & RATE_CKCTL) {
557 dsor_exp = calc_dsor_exp(clk, rate);
558 if (dsor_exp > 3)
559 dsor_exp = -EINVAL;
560 if (dsor_exp < 0)
561 return dsor_exp;
562
563 regval = omap_readw(ARM_CKCTL);
564 regval &= ~(3 << clk->rate_offset);
565 regval |= dsor_exp << clk->rate_offset;
566 regval = verify_ckctl_value(regval);
567 omap_writew(regval, ARM_CKCTL);
568 clk->rate = clk->parent->rate / (1 << dsor_exp);
569 ret = 0;
570 }
571
572 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
573 propagate_rate(clk);
574
575 return ret;
576}
577
578/*-------------------------------------------------------------------------
579 * Omap1 clock reset and init functions
580 *-------------------------------------------------------------------------*/
581
582#ifdef CONFIG_OMAP_RESET_CLOCKS
583/*
584 * Resets some clocks that may be left on from bootloader,
585 * but leaves serial clocks on. See also omap_late_clk_reset().
586 */
587static inline void omap1_early_clk_reset(void)
588{
589 //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
590}
591
592static int __init omap1_late_clk_reset(void)
593{
594 /* Turn off all unused clocks */
595 struct clk *p;
596 __u32 regval32;
597
598 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
599 regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4);
600 omap_writew(regval32, SOFT_REQ_REG);
601 omap_writew(0, SOFT_REQ_REG2);
602
603 list_for_each_entry(p, &clocks, node) {
604 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
605 p->enable_reg == 0)
606 continue;
607
608 /* Clocks in the DSP domain need api_ck. Just assume bootloader
609 * has not enabled any DSP clocks */
610 if ((u32)p->enable_reg == DSP_IDLECT2) {
611 printk(KERN_INFO "Skipping reset check for DSP domain "
612 "clock \"%s\"\n", p->name);
613 continue;
614 }
615
616 /* Is the clock already disabled? */
617 if (p->flags & ENABLE_REG_32BIT) {
618 if (p->flags & VIRTUAL_IO_ADDRESS)
619 regval32 = __raw_readl(p->enable_reg);
620 else
621 regval32 = omap_readl(p->enable_reg);
622 } else {
623 if (p->flags & VIRTUAL_IO_ADDRESS)
624 regval32 = __raw_readw(p->enable_reg);
625 else
626 regval32 = omap_readw(p->enable_reg);
627 }
628
629 if ((regval32 & (1 << p->enable_bit)) == 0)
630 continue;
631
632 /* FIXME: This clock seems to be necessary but no-one
633 * has asked for its activation. */
634 if (p == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
635 || p == &ck_dpll1out.clk // FIX: SoSSI, SSR
636 || p == &arm_gpio_ck // FIX: GPIO code for 1510
637 ) {
638 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
639 p->name);
640 continue;
641 }
642
643 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
644 p->disable(p);
645 printk(" done\n");
646 }
647
648 return 0;
649}
650late_initcall(omap1_late_clk_reset);
651
652#else
653#define omap1_early_clk_reset() {}
654#endif
655
656static struct clk_functions omap1_clk_functions = {
657 .clk_use = omap1_clk_use,
658 .clk_unuse = omap1_clk_unuse,
659 .clk_round_rate = omap1_clk_round_rate,
660 .clk_set_rate = omap1_clk_set_rate,
661};
662
663int __init omap1_clk_init(void)
664{
665 struct clk ** clkp;
666 const struct omap_clock_config *info;
667 int crystal_type = 0; /* Default 12 MHz */
668
669 omap1_early_clk_reset();
670 clk_init(&omap1_clk_functions);
671
672 /* By default all idlect1 clocks are allowed to idle */
673 arm_idlect1_mask = ~0;
674
675 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
676 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
677 clk_register(*clkp);
678 continue;
679 }
680
681 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
682 clk_register(*clkp);
683 continue;
684 }
685
686 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
687 clk_register(*clkp);
688 continue;
689 }
690 }
691
692 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
693 if (info != NULL) {
694 if (!cpu_is_omap1510())
695 crystal_type = info->system_clock_type;
696 }
697
698#if defined(CONFIG_ARCH_OMAP730)
699 ck_ref.rate = 13000000;
700#elif defined(CONFIG_ARCH_OMAP16XX)
701 if (crystal_type == 2)
702 ck_ref.rate = 19200000;
703#endif
704
705 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
706 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
707 omap_readw(ARM_CKCTL));
708
709 /* We want to be in syncronous scalable mode */
710 omap_writew(0x1000, ARM_SYSST);
711
712#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
713 /* Use values set by bootloader. Determine PLL rate and recalculate
714 * dependent clocks as if kernel had changed PLL or divisors.
715 */
716 {
717 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
718
719 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
720 if (pll_ctl_val & 0x10) {
721 /* PLL enabled, apply multiplier and divisor */
722 if (pll_ctl_val & 0xf80)
723 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
724 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
725 } else {
726 /* PLL disabled, apply bypass divisor */
727 switch (pll_ctl_val & 0xc) {
728 case 0:
729 break;
730 case 0x4:
731 ck_dpll1.rate /= 2;
732 break;
733 default:
734 ck_dpll1.rate /= 4;
735 break;
736 }
737 }
738 }
739 propagate_rate(&ck_dpll1);
740#else
741 /* Find the highest supported frequency and enable it */
742 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
743 printk(KERN_ERR "System frequencies not set. Check your config.\n");
744 /* Guess sane values (60MHz) */
745 omap_writew(0x2290, DPLL_CTL);
746 omap_writew(0x1005, ARM_CKCTL);
747 ck_dpll1.rate = 60000000;
748 propagate_rate(&ck_dpll1);
749 }
750#endif
751 /* Cache rates for clocks connected to ck_ref (not dpll1) */
752 propagate_rate(&ck_ref);
753 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
754 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
755 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
756 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
757 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
758
759#ifdef CONFIG_MACH_OMAP_PERSEUS2
760 /* Select slicer output as OMAP input clock */
761 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
762#endif
763
764 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
765 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
766
767 /* Put DSP/MPUI into reset until needed */
768 omap_writew(0, ARM_RSTCT1);
769 omap_writew(1, ARM_RSTCT2);
770 omap_writew(0x400, ARM_IDLECT1);
771
772 /*
773 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
774 * of the ARM_IDLECT2 register must be set to zero. The power-on
775 * default value of this bit is one.
776 */
777 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
778
779 /*
780 * Only enable those clocks we will need, let the drivers
781 * enable other clocks as necessary
782 */
783 clk_use(&armper_ck.clk);
784 clk_use(&armxor_ck.clk);
785 clk_use(&armtim_ck.clk); /* This should be done by timer code */
786
787 if (cpu_is_omap1510())
788 clk_enable(&arm_gpio_ck);
789
790 return 0;
791}
792
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
new file mode 100644
index 000000000000..f3bdfb50e01a
--- /dev/null
+++ b/arch/arm/mach-omap1/clock.h
@@ -0,0 +1,768 @@
1/*
2 * linux/arch/arm/mach-omap1/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
15
16static int omap1_clk_enable(struct clk * clk);
17static void omap1_clk_disable(struct clk * clk);
18static void omap1_ckctl_recalc(struct clk * clk);
19static void omap1_watchdog_recalc(struct clk * clk);
20static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
21static int omap1_clk_enable_dsp_domain(struct clk * clk);
22static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
23static void omap1_clk_disable_dsp_domain(struct clk * clk);
24static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
25static void omap1_uart_recalc(struct clk * clk);
26static int omap1_clk_enable_uart_functional(struct clk * clk);
27static void omap1_clk_disable_uart_functional(struct clk * clk);
28static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
29static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
30static void omap1_init_ext_clk(struct clk * clk);
31static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
32static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
33static int omap1_clk_use(struct clk *clk);
34static void omap1_clk_unuse(struct clk *clk);
35
36struct mpu_rate {
37 unsigned long rate;
38 unsigned long xtal;
39 unsigned long pll_rate;
40 __u16 ckctl_val;
41 __u16 dpllctl_val;
42};
43
44struct uart_clk {
45 struct clk clk;
46 unsigned long sysc_addr;
47};
48
49/* Provide a method for preventing idling some ARM IDLECT clocks */
50struct arm_idlect1_clk {
51 struct clk clk;
52 unsigned long no_idle_count;
53 __u8 idlect_shift;
54};
55
56/* ARM_CKCTL bit shifts */
57#define CKCTL_PERDIV_OFFSET 0
58#define CKCTL_LCDDIV_OFFSET 2
59#define CKCTL_ARMDIV_OFFSET 4
60#define CKCTL_DSPDIV_OFFSET 6
61#define CKCTL_TCDIV_OFFSET 8
62#define CKCTL_DSPMMUDIV_OFFSET 10
63/*#define ARM_TIMXO 12*/
64#define EN_DSPCK 13
65/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
66/* DSP_CKCTL bit shifts */
67#define CKCTL_DSPPERDIV_OFFSET 0
68
69/* ARM_IDLECT2 bit shifts */
70#define EN_WDTCK 0
71#define EN_XORPCK 1
72#define EN_PERCK 2
73#define EN_LCDCK 3
74#define EN_LBCK 4 /* Not on 1610/1710 */
75/*#define EN_HSABCK 5*/
76#define EN_APICK 6
77#define EN_TIMCK 7
78#define DMACK_REQ 8
79#define EN_GPIOCK 9 /* Not on 1610/1710 */
80/*#define EN_LBFREECK 10*/
81#define EN_CKOUT_ARM 11
82
83/* ARM_IDLECT3 bit shifts */
84#define EN_OCPI_CK 0
85#define EN_TC1_CK 2
86#define EN_TC2_CK 4
87
88/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
89#define EN_DSPTIMCK 5
90
91/* Various register defines for clock controls scattered around OMAP chip */
92#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
93#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
94#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
95#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
96#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
97#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
98#define SOFT_REQ_REG 0xfffe0834
99#define SOFT_REQ_REG2 0xfffe0880
100
101/*-------------------------------------------------------------------------
102 * Omap1 MPU rate table
103 *-------------------------------------------------------------------------*/
104static struct mpu_rate rate_table[] = {
105 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
106 * NOTE: Comment order here is different from bits in CKCTL value:
107 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
108 */
109#if defined(CONFIG_OMAP_ARM_216MHZ)
110 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
111#endif
112#if defined(CONFIG_OMAP_ARM_195MHZ)
113 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
114#endif
115#if defined(CONFIG_OMAP_ARM_192MHZ)
116 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
117 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
118 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
119 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
120 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
121#endif
122#if defined(CONFIG_OMAP_ARM_182MHZ)
123 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
124#endif
125#if defined(CONFIG_OMAP_ARM_168MHZ)
126 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
127#endif
128#if defined(CONFIG_OMAP_ARM_150MHZ)
129 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
130#endif
131#if defined(CONFIG_OMAP_ARM_120MHZ)
132 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
133#endif
134#if defined(CONFIG_OMAP_ARM_96MHZ)
135 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
136#endif
137#if defined(CONFIG_OMAP_ARM_60MHZ)
138 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
139#endif
140#if defined(CONFIG_OMAP_ARM_30MHZ)
141 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
142#endif
143 { 0, 0, 0, 0, 0 },
144};
145
146/*-------------------------------------------------------------------------
147 * Omap1 clocks
148 *-------------------------------------------------------------------------*/
149
150static struct clk ck_ref = {
151 .name = "ck_ref",
152 .rate = 12000000,
153 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
154 ALWAYS_ENABLED,
155 .enable = &omap1_clk_enable,
156 .disable = &omap1_clk_disable,
157};
158
159static struct clk ck_dpll1 = {
160 .name = "ck_dpll1",
161 .parent = &ck_ref,
162 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
163 RATE_PROPAGATES | ALWAYS_ENABLED,
164 .enable = &omap1_clk_enable,
165 .disable = &omap1_clk_disable,
166};
167
168static struct arm_idlect1_clk ck_dpll1out = {
169 .clk = {
170 .name = "ck_dpll1out",
171 .parent = &ck_dpll1,
172 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL,
173 .enable_reg = (void __iomem *)ARM_IDLECT2,
174 .enable_bit = EN_CKOUT_ARM,
175 .recalc = &followparent_recalc,
176 .enable = &omap1_clk_enable,
177 .disable = &omap1_clk_disable,
178 },
179 .idlect_shift = 12,
180};
181
182static struct clk arm_ck = {
183 .name = "arm_ck",
184 .parent = &ck_dpll1,
185 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
186 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
187 .rate_offset = CKCTL_ARMDIV_OFFSET,
188 .recalc = &omap1_ckctl_recalc,
189 .enable = &omap1_clk_enable,
190 .disable = &omap1_clk_disable,
191};
192
193static struct arm_idlect1_clk armper_ck = {
194 .clk = {
195 .name = "armper_ck",
196 .parent = &ck_dpll1,
197 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
198 RATE_CKCTL | CLOCK_IDLE_CONTROL,
199 .enable_reg = (void __iomem *)ARM_IDLECT2,
200 .enable_bit = EN_PERCK,
201 .rate_offset = CKCTL_PERDIV_OFFSET,
202 .recalc = &omap1_ckctl_recalc,
203 .enable = &omap1_clk_enable,
204 .disable = &omap1_clk_disable,
205 },
206 .idlect_shift = 2,
207};
208
209static struct clk arm_gpio_ck = {
210 .name = "arm_gpio_ck",
211 .parent = &ck_dpll1,
212 .flags = CLOCK_IN_OMAP1510,
213 .enable_reg = (void __iomem *)ARM_IDLECT2,
214 .enable_bit = EN_GPIOCK,
215 .recalc = &followparent_recalc,
216 .enable = &omap1_clk_enable,
217 .disable = &omap1_clk_disable,
218};
219
220static struct arm_idlect1_clk armxor_ck = {
221 .clk = {
222 .name = "armxor_ck",
223 .parent = &ck_ref,
224 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
225 CLOCK_IDLE_CONTROL,
226 .enable_reg = (void __iomem *)ARM_IDLECT2,
227 .enable_bit = EN_XORPCK,
228 .recalc = &followparent_recalc,
229 .enable = &omap1_clk_enable,
230 .disable = &omap1_clk_disable,
231 },
232 .idlect_shift = 1,
233};
234
235static struct arm_idlect1_clk armtim_ck = {
236 .clk = {
237 .name = "armtim_ck",
238 .parent = &ck_ref,
239 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
240 CLOCK_IDLE_CONTROL,
241 .enable_reg = (void __iomem *)ARM_IDLECT2,
242 .enable_bit = EN_TIMCK,
243 .recalc = &followparent_recalc,
244 .enable = &omap1_clk_enable,
245 .disable = &omap1_clk_disable,
246 },
247 .idlect_shift = 9,
248};
249
250static struct arm_idlect1_clk armwdt_ck = {
251 .clk = {
252 .name = "armwdt_ck",
253 .parent = &ck_ref,
254 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
255 CLOCK_IDLE_CONTROL,
256 .enable_reg = (void __iomem *)ARM_IDLECT2,
257 .enable_bit = EN_WDTCK,
258 .recalc = &omap1_watchdog_recalc,
259 .enable = &omap1_clk_enable,
260 .disable = &omap1_clk_disable,
261 },
262 .idlect_shift = 0,
263};
264
265static struct clk arminth_ck16xx = {
266 .name = "arminth_ck",
267 .parent = &arm_ck,
268 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
269 .recalc = &followparent_recalc,
270 /* Note: On 16xx the frequency can be divided by 2 by programming
271 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
272 *
273 * 1510 version is in TC clocks.
274 */
275 .enable = &omap1_clk_enable,
276 .disable = &omap1_clk_disable,
277};
278
279static struct clk dsp_ck = {
280 .name = "dsp_ck",
281 .parent = &ck_dpll1,
282 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
283 RATE_CKCTL,
284 .enable_reg = (void __iomem *)ARM_CKCTL,
285 .enable_bit = EN_DSPCK,
286 .rate_offset = CKCTL_DSPDIV_OFFSET,
287 .recalc = &omap1_ckctl_recalc,
288 .enable = &omap1_clk_enable,
289 .disable = &omap1_clk_disable,
290};
291
292static struct clk dspmmu_ck = {
293 .name = "dspmmu_ck",
294 .parent = &ck_dpll1,
295 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
296 RATE_CKCTL | ALWAYS_ENABLED,
297 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
298 .recalc = &omap1_ckctl_recalc,
299 .enable = &omap1_clk_enable,
300 .disable = &omap1_clk_disable,
301};
302
303static struct clk dspper_ck = {
304 .name = "dspper_ck",
305 .parent = &ck_dpll1,
306 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
307 RATE_CKCTL | VIRTUAL_IO_ADDRESS,
308 .enable_reg = (void __iomem *)DSP_IDLECT2,
309 .enable_bit = EN_PERCK,
310 .rate_offset = CKCTL_PERDIV_OFFSET,
311 .recalc = &omap1_ckctl_recalc_dsp_domain,
312 .set_rate = &omap1_clk_set_rate_dsp_domain,
313 .enable = &omap1_clk_enable_dsp_domain,
314 .disable = &omap1_clk_disable_dsp_domain,
315};
316
317static struct clk dspxor_ck = {
318 .name = "dspxor_ck",
319 .parent = &ck_ref,
320 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
321 VIRTUAL_IO_ADDRESS,
322 .enable_reg = (void __iomem *)DSP_IDLECT2,
323 .enable_bit = EN_XORPCK,
324 .recalc = &followparent_recalc,
325 .enable = &omap1_clk_enable_dsp_domain,
326 .disable = &omap1_clk_disable_dsp_domain,
327};
328
329static struct clk dsptim_ck = {
330 .name = "dsptim_ck",
331 .parent = &ck_ref,
332 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
333 VIRTUAL_IO_ADDRESS,
334 .enable_reg = (void __iomem *)DSP_IDLECT2,
335 .enable_bit = EN_DSPTIMCK,
336 .recalc = &followparent_recalc,
337 .enable = &omap1_clk_enable_dsp_domain,
338 .disable = &omap1_clk_disable_dsp_domain,
339};
340
341/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
342static struct arm_idlect1_clk tc_ck = {
343 .clk = {
344 .name = "tc_ck",
345 .parent = &ck_dpll1,
346 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
347 CLOCK_IN_OMAP730 | RATE_CKCTL |
348 RATE_PROPAGATES | ALWAYS_ENABLED |
349 CLOCK_IDLE_CONTROL,
350 .rate_offset = CKCTL_TCDIV_OFFSET,
351 .recalc = &omap1_ckctl_recalc,
352 .enable = &omap1_clk_enable,
353 .disable = &omap1_clk_disable,
354 },
355 .idlect_shift = 6,
356};
357
358static struct clk arminth_ck1510 = {
359 .name = "arminth_ck",
360 .parent = &tc_ck.clk,
361 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
362 .recalc = &followparent_recalc,
363 /* Note: On 1510 the frequency follows TC_CK
364 *
365 * 16xx version is in MPU clocks.
366 */
367 .enable = &omap1_clk_enable,
368 .disable = &omap1_clk_disable,
369};
370
371static struct clk tipb_ck = {
372 /* No-idle controlled by "tc_ck" */
373 .name = "tibp_ck",
374 .parent = &tc_ck.clk,
375 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
376 .recalc = &followparent_recalc,
377 .enable = &omap1_clk_enable,
378 .disable = &omap1_clk_disable,
379};
380
381static struct clk l3_ocpi_ck = {
382 /* No-idle controlled by "tc_ck" */
383 .name = "l3_ocpi_ck",
384 .parent = &tc_ck.clk,
385 .flags = CLOCK_IN_OMAP16XX,
386 .enable_reg = (void __iomem *)ARM_IDLECT3,
387 .enable_bit = EN_OCPI_CK,
388 .recalc = &followparent_recalc,
389 .enable = &omap1_clk_enable,
390 .disable = &omap1_clk_disable,
391};
392
393static struct clk tc1_ck = {
394 .name = "tc1_ck",
395 .parent = &tc_ck.clk,
396 .flags = CLOCK_IN_OMAP16XX,
397 .enable_reg = (void __iomem *)ARM_IDLECT3,
398 .enable_bit = EN_TC1_CK,
399 .recalc = &followparent_recalc,
400 .enable = &omap1_clk_enable,
401 .disable = &omap1_clk_disable,
402};
403
404static struct clk tc2_ck = {
405 .name = "tc2_ck",
406 .parent = &tc_ck.clk,
407 .flags = CLOCK_IN_OMAP16XX,
408 .enable_reg = (void __iomem *)ARM_IDLECT3,
409 .enable_bit = EN_TC2_CK,
410 .recalc = &followparent_recalc,
411 .enable = &omap1_clk_enable,
412 .disable = &omap1_clk_disable,
413};
414
415static struct clk dma_ck = {
416 /* No-idle controlled by "tc_ck" */
417 .name = "dma_ck",
418 .parent = &tc_ck.clk,
419 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
420 ALWAYS_ENABLED,
421 .recalc = &followparent_recalc,
422 .enable = &omap1_clk_enable,
423 .disable = &omap1_clk_disable,
424};
425
426static struct clk dma_lcdfree_ck = {
427 .name = "dma_lcdfree_ck",
428 .parent = &tc_ck.clk,
429 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
430 .recalc = &followparent_recalc,
431 .enable = &omap1_clk_enable,
432 .disable = &omap1_clk_disable,
433};
434
435static struct arm_idlect1_clk api_ck = {
436 .clk = {
437 .name = "api_ck",
438 .parent = &tc_ck.clk,
439 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
440 CLOCK_IDLE_CONTROL,
441 .enable_reg = (void __iomem *)ARM_IDLECT2,
442 .enable_bit = EN_APICK,
443 .recalc = &followparent_recalc,
444 .enable = &omap1_clk_enable,
445 .disable = &omap1_clk_disable,
446 },
447 .idlect_shift = 8,
448};
449
450static struct arm_idlect1_clk lb_ck = {
451 .clk = {
452 .name = "lb_ck",
453 .parent = &tc_ck.clk,
454 .flags = CLOCK_IN_OMAP1510 | CLOCK_IDLE_CONTROL,
455 .enable_reg = (void __iomem *)ARM_IDLECT2,
456 .enable_bit = EN_LBCK,
457 .recalc = &followparent_recalc,
458 .enable = &omap1_clk_enable,
459 .disable = &omap1_clk_disable,
460 },
461 .idlect_shift = 4,
462};
463
464static struct clk rhea1_ck = {
465 .name = "rhea1_ck",
466 .parent = &tc_ck.clk,
467 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
468 .recalc = &followparent_recalc,
469 .enable = &omap1_clk_enable,
470 .disable = &omap1_clk_disable,
471};
472
473static struct clk rhea2_ck = {
474 .name = "rhea2_ck",
475 .parent = &tc_ck.clk,
476 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
477 .recalc = &followparent_recalc,
478 .enable = &omap1_clk_enable,
479 .disable = &omap1_clk_disable,
480};
481
482static struct clk lcd_ck_16xx = {
483 .name = "lcd_ck",
484 .parent = &ck_dpll1,
485 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
486 .enable_reg = (void __iomem *)ARM_IDLECT2,
487 .enable_bit = EN_LCDCK,
488 .rate_offset = CKCTL_LCDDIV_OFFSET,
489 .recalc = &omap1_ckctl_recalc,
490 .enable = &omap1_clk_enable,
491 .disable = &omap1_clk_disable,
492};
493
494static struct arm_idlect1_clk lcd_ck_1510 = {
495 .clk = {
496 .name = "lcd_ck",
497 .parent = &ck_dpll1,
498 .flags = CLOCK_IN_OMAP1510 | RATE_CKCTL |
499 CLOCK_IDLE_CONTROL,
500 .enable_reg = (void __iomem *)ARM_IDLECT2,
501 .enable_bit = EN_LCDCK,
502 .rate_offset = CKCTL_LCDDIV_OFFSET,
503 .recalc = &omap1_ckctl_recalc,
504 .enable = &omap1_clk_enable,
505 .disable = &omap1_clk_disable,
506 },
507 .idlect_shift = 3,
508};
509
510static struct clk uart1_1510 = {
511 .name = "uart1_ck",
512 /* Direct from ULPD, no real parent */
513 .parent = &armper_ck.clk,
514 .rate = 12000000,
515 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT |
516 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
517 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
518 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
519 .set_rate = &omap1_set_uart_rate,
520 .recalc = &omap1_uart_recalc,
521 .enable = &omap1_clk_enable,
522 .disable = &omap1_clk_disable,
523};
524
525static struct uart_clk uart1_16xx = {
526 .clk = {
527 .name = "uart1_ck",
528 /* Direct from ULPD, no real parent */
529 .parent = &armper_ck.clk,
530 .rate = 48000000,
531 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
532 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
533 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
534 .enable_bit = 29,
535 .enable = &omap1_clk_enable_uart_functional,
536 .disable = &omap1_clk_disable_uart_functional,
537 },
538 .sysc_addr = 0xfffb0054,
539};
540
541static struct clk uart2_ck = {
542 .name = "uart2_ck",
543 /* Direct from ULPD, no real parent */
544 .parent = &armper_ck.clk,
545 .rate = 12000000,
546 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
547 ENABLE_REG_32BIT | ALWAYS_ENABLED |
548 CLOCK_NO_IDLE_PARENT,
549 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
550 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
551 .set_rate = &omap1_set_uart_rate,
552 .recalc = &omap1_uart_recalc,
553 .enable = &omap1_clk_enable,
554 .disable = &omap1_clk_disable,
555};
556
557static struct clk uart3_1510 = {
558 .name = "uart3_ck",
559 /* Direct from ULPD, no real parent */
560 .parent = &armper_ck.clk,
561 .rate = 12000000,
562 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT |
563 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
564 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
565 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
566 .set_rate = &omap1_set_uart_rate,
567 .recalc = &omap1_uart_recalc,
568 .enable = &omap1_clk_enable,
569 .disable = &omap1_clk_disable,
570};
571
572static struct uart_clk uart3_16xx = {
573 .clk = {
574 .name = "uart3_ck",
575 /* Direct from ULPD, no real parent */
576 .parent = &armper_ck.clk,
577 .rate = 48000000,
578 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
579 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
580 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
581 .enable_bit = 31,
582 .enable = &omap1_clk_enable_uart_functional,
583 .disable = &omap1_clk_disable_uart_functional,
584 },
585 .sysc_addr = 0xfffb9854,
586};
587
588static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
589 .name = "usb_clko",
590 /* Direct from ULPD, no parent */
591 .rate = 6000000,
592 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
593 RATE_FIXED | ENABLE_REG_32BIT,
594 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
595 .enable_bit = USB_MCLK_EN_BIT,
596 .enable = &omap1_clk_enable,
597 .disable = &omap1_clk_disable,
598};
599
600static struct clk usb_hhc_ck1510 = {
601 .name = "usb_hhc_ck",
602 /* Direct from ULPD, no parent */
603 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
604 .flags = CLOCK_IN_OMAP1510 |
605 RATE_FIXED | ENABLE_REG_32BIT,
606 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
607 .enable_bit = USB_HOST_HHC_UHOST_EN,
608 .enable = &omap1_clk_enable,
609 .disable = &omap1_clk_disable,
610};
611
612static struct clk usb_hhc_ck16xx = {
613 .name = "usb_hhc_ck",
614 /* Direct from ULPD, no parent */
615 .rate = 48000000,
616 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
617 .flags = CLOCK_IN_OMAP16XX |
618 RATE_FIXED | ENABLE_REG_32BIT,
619 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
620 .enable_bit = 8 /* UHOST_EN */,
621 .enable = &omap1_clk_enable,
622 .disable = &omap1_clk_disable,
623};
624
625static struct clk usb_dc_ck = {
626 .name = "usb_dc_ck",
627 /* Direct from ULPD, no parent */
628 .rate = 48000000,
629 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
630 .enable_reg = (void __iomem *)SOFT_REQ_REG,
631 .enable_bit = 4,
632 .enable = &omap1_clk_enable,
633 .disable = &omap1_clk_disable,
634};
635
636static struct clk mclk_1510 = {
637 .name = "mclk",
638 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
639 .rate = 12000000,
640 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
641 .enable = &omap1_clk_enable,
642 .disable = &omap1_clk_disable,
643};
644
645static struct clk mclk_16xx = {
646 .name = "mclk",
647 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
648 .flags = CLOCK_IN_OMAP16XX,
649 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
650 .enable_bit = COM_ULPD_PLL_CLK_REQ,
651 .set_rate = &omap1_set_ext_clk_rate,
652 .round_rate = &omap1_round_ext_clk_rate,
653 .init = &omap1_init_ext_clk,
654 .enable = &omap1_clk_enable,
655 .disable = &omap1_clk_disable,
656};
657
658static struct clk bclk_1510 = {
659 .name = "bclk",
660 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
661 .rate = 12000000,
662 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
663 .enable = &omap1_clk_enable,
664 .disable = &omap1_clk_disable,
665};
666
667static struct clk bclk_16xx = {
668 .name = "bclk",
669 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
670 .flags = CLOCK_IN_OMAP16XX,
671 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
672 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
673 .set_rate = &omap1_set_ext_clk_rate,
674 .round_rate = &omap1_round_ext_clk_rate,
675 .init = &omap1_init_ext_clk,
676 .enable = &omap1_clk_enable,
677 .disable = &omap1_clk_disable,
678};
679
680static struct clk mmc1_ck = {
681 .name = "mmc1_ck",
682 /* Functional clock is direct from ULPD, interface clock is ARMPER */
683 .parent = &armper_ck.clk,
684 .rate = 48000000,
685 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
686 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
687 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
688 .enable_bit = 23,
689 .enable = &omap1_clk_enable,
690 .disable = &omap1_clk_disable,
691};
692
693static struct clk mmc2_ck = {
694 .name = "mmc2_ck",
695 /* Functional clock is direct from ULPD, interface clock is ARMPER */
696 .parent = &armper_ck.clk,
697 .rate = 48000000,
698 .flags = CLOCK_IN_OMAP16XX |
699 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
700 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
701 .enable_bit = 20,
702 .enable = &omap1_clk_enable,
703 .disable = &omap1_clk_disable,
704};
705
706static struct clk virtual_ck_mpu = {
707 .name = "mpu",
708 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
709 VIRTUAL_CLOCK | ALWAYS_ENABLED,
710 .parent = &arm_ck, /* Is smarter alias for */
711 .recalc = &followparent_recalc,
712 .set_rate = &omap1_select_table_rate,
713 .round_rate = &omap1_round_to_table_rate,
714 .enable = &omap1_clk_enable,
715 .disable = &omap1_clk_disable,
716};
717
718static struct clk * onchip_clks[] = {
719 /* non-ULPD clocks */
720 &ck_ref,
721 &ck_dpll1,
722 /* CK_GEN1 clocks */
723 &ck_dpll1out.clk,
724 &arm_ck,
725 &armper_ck.clk,
726 &arm_gpio_ck,
727 &armxor_ck.clk,
728 &armtim_ck.clk,
729 &armwdt_ck.clk,
730 &arminth_ck1510, &arminth_ck16xx,
731 /* CK_GEN2 clocks */
732 &dsp_ck,
733 &dspmmu_ck,
734 &dspper_ck,
735 &dspxor_ck,
736 &dsptim_ck,
737 /* CK_GEN3 clocks */
738 &tc_ck.clk,
739 &tipb_ck,
740 &l3_ocpi_ck,
741 &tc1_ck,
742 &tc2_ck,
743 &dma_ck,
744 &dma_lcdfree_ck,
745 &api_ck.clk,
746 &lb_ck.clk,
747 &rhea1_ck,
748 &rhea2_ck,
749 &lcd_ck_16xx,
750 &lcd_ck_1510.clk,
751 /* ULPD clocks */
752 &uart1_1510,
753 &uart1_16xx.clk,
754 &uart2_ck,
755 &uart3_1510,
756 &uart3_16xx.clk,
757 &usb_clko,
758 &usb_hhc_ck1510, &usb_hhc_ck16xx,
759 &usb_dc_ck,
760 &mclk_1510, &mclk_16xx,
761 &bclk_1510, &bclk_16xx,
762 &mmc1_ck,
763 &mmc2_ck,
764 /* Virtual clocks */
765 &virtual_ck_mpu,
766};
767
768#endif
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 3c5d901efeaa..ecbc47514adc 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -25,56 +25,7 @@
25#include <asm/arch/mux.h> 25#include <asm/arch/mux.h>
26#include <asm/arch/gpio.h> 26#include <asm/arch/gpio.h>
27 27
28 28extern void omap_nop_release(struct device *dev);
29static void omap_nop_release(struct device *dev)
30{
31 /* Nothing */
32}
33
34/*-------------------------------------------------------------------------*/
35
36#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
37
38#define OMAP_I2C_BASE 0xfffb3800
39
40static struct resource i2c_resources[] = {
41 {
42 .start = OMAP_I2C_BASE,
43 .end = OMAP_I2C_BASE + 0x3f,
44 .flags = IORESOURCE_MEM,
45 },
46 {
47 .start = INT_I2C,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52/* DMA not used; works around erratum writing to non-empty i2c fifo */
53
54static struct platform_device omap_i2c_device = {
55 .name = "i2c_omap",
56 .id = -1,
57 .dev = {
58 .release = omap_nop_release,
59 },
60 .num_resources = ARRAY_SIZE(i2c_resources),
61 .resource = i2c_resources,
62};
63
64static void omap_init_i2c(void)
65{
66 /* FIXME define and use a boot tag, in case of boards that
67 * either don't wire up I2C, or chips that mux it differently...
68 * it can include clocking and address info, maybe more.
69 */
70 omap_cfg_reg(I2C_SCL);
71 omap_cfg_reg(I2C_SDA);
72
73 (void) platform_device_register(&omap_i2c_device);
74}
75#else
76static inline void omap_init_i2c(void) {}
77#endif
78 29
79/*-------------------------------------------------------------------------*/ 30/*-------------------------------------------------------------------------*/
80 31
@@ -110,137 +61,6 @@ static inline void omap_init_irda(void) {}
110 61
111/*-------------------------------------------------------------------------*/ 62/*-------------------------------------------------------------------------*/
112 63
113#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
114
115#define OMAP_MMC1_BASE 0xfffb7800
116#define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */
117
118static struct omap_mmc_conf mmc1_conf;
119
120static u64 mmc1_dmamask = 0xffffffff;
121
122static struct resource mmc1_resources[] = {
123 {
124 .start = IO_ADDRESS(OMAP_MMC1_BASE),
125 .end = IO_ADDRESS(OMAP_MMC1_BASE) + 0x7f,
126 .flags = IORESOURCE_MEM,
127 },
128 {
129 .start = INT_MMC,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
134static struct platform_device mmc_omap_device1 = {
135 .name = "mmci-omap",
136 .id = 1,
137 .dev = {
138 .release = omap_nop_release,
139 .dma_mask = &mmc1_dmamask,
140 .platform_data = &mmc1_conf,
141 },
142 .num_resources = ARRAY_SIZE(mmc1_resources),
143 .resource = mmc1_resources,
144};
145
146#ifdef CONFIG_ARCH_OMAP16XX
147
148static struct omap_mmc_conf mmc2_conf;
149
150static u64 mmc2_dmamask = 0xffffffff;
151
152static struct resource mmc2_resources[] = {
153 {
154 .start = IO_ADDRESS(OMAP_MMC2_BASE),
155 .end = IO_ADDRESS(OMAP_MMC2_BASE) + 0x7f,
156 .flags = IORESOURCE_MEM,
157 },
158 {
159 .start = INT_1610_MMC2,
160 .flags = IORESOURCE_IRQ,
161 },
162};
163
164static struct platform_device mmc_omap_device2 = {
165 .name = "mmci-omap",
166 .id = 2,
167 .dev = {
168 .release = omap_nop_release,
169 .dma_mask = &mmc2_dmamask,
170 .platform_data = &mmc2_conf,
171 },
172 .num_resources = ARRAY_SIZE(mmc2_resources),
173 .resource = mmc2_resources,
174};
175#endif
176
177static void __init omap_init_mmc(void)
178{
179 const struct omap_mmc_config *mmc_conf;
180 const struct omap_mmc_conf *mmc;
181
182 /* NOTE: assumes MMC was never (wrongly) enabled */
183 mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
184 if (!mmc_conf)
185 return;
186
187 /* block 1 is always available and has just one pinout option */
188 mmc = &mmc_conf->mmc[0];
189 if (mmc->enabled) {
190 omap_cfg_reg(MMC_CMD);
191 omap_cfg_reg(MMC_CLK);
192 omap_cfg_reg(MMC_DAT0);
193 if (cpu_is_omap1710()) {
194 omap_cfg_reg(M15_1710_MMC_CLKI);
195 omap_cfg_reg(P19_1710_MMC_CMDDIR);
196 omap_cfg_reg(P20_1710_MMC_DATDIR0);
197 }
198 if (mmc->wire4) {
199 omap_cfg_reg(MMC_DAT1);
200 /* NOTE: DAT2 can be on W10 (here) or M15 */
201 if (!mmc->nomux)
202 omap_cfg_reg(MMC_DAT2);
203 omap_cfg_reg(MMC_DAT3);
204 }
205 mmc1_conf = *mmc;
206 (void) platform_device_register(&mmc_omap_device1);
207 }
208
209#ifdef CONFIG_ARCH_OMAP16XX
210 /* block 2 is on newer chips, and has many pinout options */
211 mmc = &mmc_conf->mmc[1];
212 if (mmc->enabled) {
213 if (!mmc->nomux) {
214 omap_cfg_reg(Y8_1610_MMC2_CMD);
215 omap_cfg_reg(Y10_1610_MMC2_CLK);
216 omap_cfg_reg(R18_1610_MMC2_CLKIN);
217 omap_cfg_reg(W8_1610_MMC2_DAT0);
218 if (mmc->wire4) {
219 omap_cfg_reg(V8_1610_MMC2_DAT1);
220 omap_cfg_reg(W15_1610_MMC2_DAT2);
221 omap_cfg_reg(R10_1610_MMC2_DAT3);
222 }
223
224 /* These are needed for the level shifter */
225 omap_cfg_reg(V9_1610_MMC2_CMDDIR);
226 omap_cfg_reg(V5_1610_MMC2_DATDIR0);
227 omap_cfg_reg(W19_1610_MMC2_DATDIR1);
228 }
229
230 /* Feedback clock must be set on OMAP-1710 MMC2 */
231 if (cpu_is_omap1710())
232 omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
233 MOD_CONF_CTRL_1);
234 mmc2_conf = *mmc;
235 (void) platform_device_register(&mmc_omap_device2);
236 }
237#endif
238 return;
239}
240#else
241static inline void omap_init_mmc(void) {}
242#endif
243
244#if defined(CONFIG_OMAP_RTC) || defined(CONFIG_OMAP_RTC) 64#if defined(CONFIG_OMAP_RTC) || defined(CONFIG_OMAP_RTC)
245 65
246#define OMAP_RTC_BASE 0xfffb4800 66#define OMAP_RTC_BASE 0xfffb4800
@@ -279,38 +99,6 @@ static void omap_init_rtc(void)
279static inline void omap_init_rtc(void) {} 99static inline void omap_init_rtc(void) {}
280#endif 100#endif
281 101
282/*-------------------------------------------------------------------------*/
283
284#if defined(CONFIG_OMAP16XX_WATCHDOG) || defined(CONFIG_OMAP16XX_WATCHDOG_MODULE)
285
286#define OMAP_WDT_BASE 0xfffeb000
287
288static struct resource wdt_resources[] = {
289 {
290 .start = OMAP_WDT_BASE,
291 .end = OMAP_WDT_BASE + 0x4f,
292 .flags = IORESOURCE_MEM,
293 },
294};
295
296static struct platform_device omap_wdt_device = {
297 .name = "omap1610_wdt",
298 .id = -1,
299 .dev = {
300 .release = omap_nop_release,
301 },
302 .num_resources = ARRAY_SIZE(wdt_resources),
303 .resource = wdt_resources,
304};
305
306static void omap_init_wdt(void)
307{
308 (void) platform_device_register(&omap_wdt_device);
309}
310#else
311static inline void omap_init_wdt(void) {}
312#endif
313
314 102
315/*-------------------------------------------------------------------------*/ 103/*-------------------------------------------------------------------------*/
316 104
@@ -334,18 +122,15 @@ static inline void omap_init_wdt(void) {}
334 * may be handled by the boot loader, and drivers should expect it will 122 * may be handled by the boot loader, and drivers should expect it will
335 * normally have been done by the time they're probed. 123 * normally have been done by the time they're probed.
336 */ 124 */
337static int __init omap_init_devices(void) 125static int __init omap1_init_devices(void)
338{ 126{
339 /* please keep these calls, and their implementations above, 127 /* please keep these calls, and their implementations above,
340 * in alphabetical order so they're easier to sort through. 128 * in alphabetical order so they're easier to sort through.
341 */ 129 */
342 omap_init_i2c();
343 omap_init_irda(); 130 omap_init_irda();
344 omap_init_mmc();
345 omap_init_rtc(); 131 omap_init_rtc();
346 omap_init_wdt();
347 132
348 return 0; 133 return 0;
349} 134}
350arch_initcall(omap_init_devices); 135arch_initcall(omap1_init_devices);
351 136
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index 986c3b7e09bb..5c637c048368 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -18,6 +18,13 @@
18 18
19#include <asm/io.h> 19#include <asm/io.h>
20 20
21#define OMAP_DIE_ID_0 0xfffe1800
22#define OMAP_DIE_ID_1 0xfffe1804
23#define OMAP_PRODUCTION_ID_0 0xfffe2000
24#define OMAP_PRODUCTION_ID_1 0xfffe2004
25#define OMAP32_ID_0 0xfffed400
26#define OMAP32_ID_1 0xfffed404
27
21struct omap_id { 28struct omap_id {
22 u16 jtag_id; /* Used to determine OMAP type */ 29 u16 jtag_id; /* Used to determine OMAP type */
23 u8 die_rev; /* Processor revision */ 30 u8 die_rev; /* Processor revision */
@@ -27,6 +34,7 @@ struct omap_id {
27 34
28/* Register values to detect the OMAP version */ 35/* Register values to detect the OMAP version */
29static struct omap_id omap_ids[] __initdata = { 36static struct omap_id omap_ids[] __initdata = {
37 { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
30 { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100}, 38 { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
31 { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300}, 39 { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
32 { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000}, 40 { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
@@ -164,6 +172,7 @@ void __init omap_check_revision(void)
164 case 0x07: 172 case 0x07:
165 system_rev |= 0x07; 173 system_rev |= 0x07;
166 break; 174 break;
175 case 0x03:
167 case 0x15: 176 case 0x15:
168 system_rev |= 0x15; 177 system_rev |= 0x15;
169 break; 178 break;
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 79fb86535ebc..a7a19f75b9e1 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -15,9 +15,10 @@
15 15
16#include <asm/mach/map.h> 16#include <asm/mach/map.h>
17#include <asm/io.h> 17#include <asm/io.h>
18#include <asm/arch/mux.h>
18#include <asm/arch/tc.h> 19#include <asm/arch/tc.h>
19 20
20extern int clk_init(void); 21extern int omap1_clk_init(void);
21extern void omap_check_revision(void); 22extern void omap_check_revision(void);
22extern void omap_sram_init(void); 23extern void omap_sram_init(void);
23 24
@@ -50,7 +51,7 @@ static struct map_desc omap730_io_desc[] __initdata = {
50}; 51};
51#endif 52#endif
52 53
53#ifdef CONFIG_ARCH_OMAP1510 54#ifdef CONFIG_ARCH_OMAP15XX
54static struct map_desc omap1510_io_desc[] __initdata = { 55static struct map_desc omap1510_io_desc[] __initdata = {
55 { 56 {
56 .virtual = OMAP1510_DSP_BASE, 57 .virtual = OMAP1510_DSP_BASE,
@@ -98,7 +99,7 @@ static void __init _omap_map_io(void)
98 iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); 99 iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
99 } 100 }
100#endif 101#endif
101#ifdef CONFIG_ARCH_OMAP1510 102#ifdef CONFIG_ARCH_OMAP15XX
102 if (cpu_is_omap1510()) { 103 if (cpu_is_omap1510()) {
103 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); 104 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
104 } 105 }
@@ -119,7 +120,7 @@ static void __init _omap_map_io(void)
119 120
120 /* Must init clocks early to assure that timer interrupt works 121 /* Must init clocks early to assure that timer interrupt works
121 */ 122 */
122 clk_init(); 123 omap1_clk_init();
123} 124}
124 125
125/* 126/*
@@ -127,7 +128,9 @@ static void __init _omap_map_io(void)
127 */ 128 */
128void __init omap_map_common_io(void) 129void __init omap_map_common_io(void)
129{ 130{
130 if (!initialized) 131 if (!initialized) {
131 _omap_map_io(); 132 _omap_map_io();
133 omap1_mux_init();
134 }
132} 135}
133 136
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 192ce6055faa..ed65a7d2e941 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -47,6 +47,7 @@
47#include <asm/irq.h> 47#include <asm/irq.h>
48#include <asm/mach/irq.h> 48#include <asm/mach/irq.h>
49#include <asm/arch/gpio.h> 49#include <asm/arch/gpio.h>
50#include <asm/arch/cpu.h>
50 51
51#include <asm/io.h> 52#include <asm/io.h>
52 53
@@ -147,11 +148,15 @@ static struct omap_irq_bank omap730_irq_banks[] = {
147}; 148};
148#endif 149#endif
149 150
150#ifdef CONFIG_ARCH_OMAP1510 151#ifdef CONFIG_ARCH_OMAP15XX
151static struct omap_irq_bank omap1510_irq_banks[] = { 152static struct omap_irq_bank omap1510_irq_banks[] = {
152 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, 153 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
153 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, 154 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
154}; 155};
156static struct omap_irq_bank omap310_irq_banks[] = {
157 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
158 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
159};
155#endif 160#endif
156 161
157#if defined(CONFIG_ARCH_OMAP16XX) 162#if defined(CONFIG_ARCH_OMAP16XX)
@@ -181,11 +186,15 @@ void __init omap_init_irq(void)
181 irq_bank_count = ARRAY_SIZE(omap730_irq_banks); 186 irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
182 } 187 }
183#endif 188#endif
184#ifdef CONFIG_ARCH_OMAP1510 189#ifdef CONFIG_ARCH_OMAP15XX
185 if (cpu_is_omap1510()) { 190 if (cpu_is_omap1510()) {
186 irq_banks = omap1510_irq_banks; 191 irq_banks = omap1510_irq_banks;
187 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); 192 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
188 } 193 }
194 if (cpu_is_omap310()) {
195 irq_banks = omap310_irq_banks;
196 irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
197 }
189#endif 198#endif
190#if defined(CONFIG_ARCH_OMAP16XX) 199#if defined(CONFIG_ARCH_OMAP16XX)
191 if (cpu_is_omap16xx()) { 200 if (cpu_is_omap16xx()) {
@@ -226,9 +235,11 @@ void __init omap_init_irq(void)
226 } 235 }
227 236
228 /* Unmask level 2 handler */ 237 /* Unmask level 2 handler */
229 if (cpu_is_omap730()) { 238
239 if (cpu_is_omap730())
230 omap_unmask_irq(INT_730_IH2_IRQ); 240 omap_unmask_irq(INT_730_IH2_IRQ);
231 } else { 241 else if (cpu_is_omap1510())
232 omap_unmask_irq(INT_IH2_IRQ); 242 omap_unmask_irq(INT_1510_IH2_IRQ);
233 } 243 else if (cpu_is_omap16xx())
244 omap_unmask_irq(INT_1610_IH2_IRQ);
234} 245}
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index 399010c14036..650650815915 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -18,6 +18,7 @@
18#include <asm/hardware.h> 18#include <asm/hardware.h>
19#include <asm/leds.h> 19#include <asm/leds.h>
20#include <asm/system.h> 20#include <asm/system.h>
21#include <asm/mach-types.h>
21 22
22#include <asm/arch/fpga.h> 23#include <asm/arch/fpga.h>
23#include <asm/arch/gpio.h> 24#include <asm/arch/gpio.h>
@@ -63,14 +64,19 @@ void h2p2_dbg_leds_event(led_event_t evt)
63 case led_stop: 64 case led_stop:
64 case led_halted: 65 case led_halted:
65 /* all leds off during suspend or shutdown */ 66 /* all leds off during suspend or shutdown */
66 omap_set_gpio_dataout(GPIO_TIMER, 0); 67
67 omap_set_gpio_dataout(GPIO_IDLE, 0); 68 if (! machine_is_omap_perseus2()) {
69 omap_set_gpio_dataout(GPIO_TIMER, 0);
70 omap_set_gpio_dataout(GPIO_IDLE, 0);
71 }
72
68 __raw_writew(~0, &fpga->leds); 73 __raw_writew(~0, &fpga->leds);
69 led_state &= ~LED_STATE_ENABLED; 74 led_state &= ~LED_STATE_ENABLED;
70 if (evt == led_halted) { 75 if (evt == led_halted) {
71 iounmap(fpga); 76 iounmap(fpga);
72 fpga = NULL; 77 fpga = NULL;
73 } 78 }
79
74 goto done; 80 goto done;
75 81
76 case led_claim: 82 case led_claim:
@@ -85,18 +91,37 @@ void h2p2_dbg_leds_event(led_event_t evt)
85#ifdef CONFIG_LEDS_TIMER 91#ifdef CONFIG_LEDS_TIMER
86 case led_timer: 92 case led_timer:
87 led_state ^= LED_TIMER_ON; 93 led_state ^= LED_TIMER_ON;
88 omap_set_gpio_dataout(GPIO_TIMER, led_state & LED_TIMER_ON); 94
89 goto done; 95 if (machine_is_omap_perseus2())
96 hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
97 else {
98 omap_set_gpio_dataout(GPIO_TIMER, led_state & LED_TIMER_ON);
99 goto done;
100 }
101
102 break;
90#endif 103#endif
91 104
92#ifdef CONFIG_LEDS_CPU 105#ifdef CONFIG_LEDS_CPU
93 case led_idle_start: 106 case led_idle_start:
94 omap_set_gpio_dataout(GPIO_IDLE, 1); 107 if (machine_is_omap_perseus2())
95 goto done; 108 hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
109 else {
110 omap_set_gpio_dataout(GPIO_IDLE, 1);
111 goto done;
112 }
113
114 break;
96 115
97 case led_idle_end: 116 case led_idle_end:
98 omap_set_gpio_dataout(GPIO_IDLE, 0); 117 if (machine_is_omap_perseus2())
99 goto done; 118 hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
119 else {
120 omap_set_gpio_dataout(GPIO_IDLE, 0);
121 goto done;
122 }
123
124 break;
100#endif 125#endif
101 126
102 case led_green_on: 127 case led_green_on:
@@ -135,7 +160,7 @@ void h2p2_dbg_leds_event(led_event_t evt)
135 /* 160 /*
136 * Actually burn the LEDs 161 * Actually burn the LEDs
137 */ 162 */
138 if (led_state & LED_STATE_CLAIMED) 163 if (led_state & LED_STATE_ENABLED)
139 __raw_writew(~hw_led_state, &fpga->leds); 164 __raw_writew(~hw_led_state, &fpga->leds);
140 165
141done: 166done:
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
index 5c6b1bb6e722..3f9dcac4fd41 100644
--- a/arch/arm/mach-omap1/leds.c
+++ b/arch/arm/mach-omap1/leds.c
@@ -33,7 +33,6 @@ omap_leds_init(void)
33 33
34 if (machine_is_omap_h2() 34 if (machine_is_omap_h2()
35 || machine_is_omap_h3() 35 || machine_is_omap_h3()
36 || machine_is_omap_perseus2()
37#ifdef CONFIG_OMAP_OSK_MISTRAL 36#ifdef CONFIG_OMAP_OSK_MISTRAL
38 || machine_is_omap_osk() 37 || machine_is_omap_osk()
39#endif 38#endif
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
new file mode 100644
index 000000000000..d4b8d624e742
--- /dev/null
+++ b/arch/arm/mach-omap1/mux.c
@@ -0,0 +1,289 @@
1/*
2 * linux/arch/arm/mach-omap1/mux.c
3 *
4 * OMAP1 pin multiplexing configurations
5 *
6 * Copyright (C) 2003 - 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25#include <linux/config.h>
26#include <linux/module.h>
27#include <linux/init.h>
28#include <asm/system.h>
29#include <asm/io.h>
30#include <linux/spinlock.h>
31
32#include <asm/arch/mux.h>
33
34#ifdef CONFIG_OMAP_MUX
35
36#ifdef CONFIG_ARCH_OMAP730
37struct pin_config __initdata_or_module omap730_pins[] = {
38MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 0, 20, 1, NA, 0, 0)
39MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 0, 24, 1, NA, 0, 0)
40MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 0, 28, 1, NA, 0, 0)
41MUX_CFG_730("F3_730_KBR3", 13, 1, 0, 0, 0, 1, NA, 0, 0)
42MUX_CFG_730("D2_730_KBR4", 13, 5, 0, 0, 4, 1, NA, 0, 0)
43MUX_CFG_730("C2_730_KBC0", 13, 9, 0, 0, 8, 1, NA, 0, 0)
44MUX_CFG_730("D3_730_KBC1", 13, 13, 0, 0, 12, 1, NA, 0, 0)
45MUX_CFG_730("E4_730_KBC2", 13, 17, 0, 0, 16, 1, NA, 0, 0)
46MUX_CFG_730("F4_730_KBC3", 13, 21, 0, 0, 20, 1, NA, 0, 0)
47MUX_CFG_730("E3_730_KBC4", 13, 25, 0, 0, 24, 1, NA, 0, 0)
48};
49#endif
50
51#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
52struct pin_config __initdata_or_module omap1xxx_pins[] = {
53/*
54 * description mux mode mux pull pull pull pu_pd pu dbg
55 * reg offset mode reg bit ena reg
56 */
57MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
58MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
59
60/* UART2 (COM_UART_GATING), conflicts with USB2 */
61MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
62MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
63MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
64MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
65
66/* UART3 (GIGA_UART_GATING) */
67MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
68MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
69MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
70MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
71MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
72MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
73MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
74
75/* PWT & PWL, conflicts with UART3 */
76MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
77MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
78
79/* USB internal master generic */
80MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
81MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
82/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
83MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
84MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
85MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
86MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
87
88/* USB1 master */
89MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
90MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
91MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
92MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
93MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
94MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
95MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
96MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
97MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
98MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
99MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
100
101/* USB2 master */
102MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
103MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
104MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
105MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
106MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
107MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
108MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
109
110/* OMAP-1510 GPIO */
111MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
112MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
113MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
114
115/* OMAP1610 GPIO */
116MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
117MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
118
119/* OMAP-1710 GPIO */
120MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
121MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
122MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
123MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
124
125/* MPUIO */
126MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
127MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
128MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
129MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
130
131MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
132MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
133MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
134MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
135MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
136MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
137MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
138MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
139MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
140
141/* MCBSP2 */
142MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
143MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
144MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
145MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
146MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
147MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
148
149/* MCBSP3 NOTE: Mode must 1 for clock */
150MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
151
152/* Misc ballouts */
153MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
154MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
155
156/* OMAP-1610 MMC2 */
157MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
158MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
159MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
160MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
161MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
162MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
163MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
164MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
165MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
166MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
167
168/* OMAP-1610 External Trace Interface */
169MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
170MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
171MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
172MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
173MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
174MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
175
176/* OMAP16XX GPIO */
177MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
178MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
179MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
180MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
181MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
182MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
183MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
184MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
185MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
186MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
187MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
188MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
189MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
190
191/* OMAP-1610 uWire */
192MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
193MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
194MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
195MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
196MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
197MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
198
199/* OMAP-1610 Flash */
200MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
201MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
202
203/* First MMC interface, same on 1510, 1610 and 1710 */
204MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
205MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
206MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
207MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
208MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
209MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
210MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
211MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
212MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
213
214/* OMAP-1610 USB0 alternate configuration */
215MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
216MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
217MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
218MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
219MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
220MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
221MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
222MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
223
224/* USB2 interface */
225MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
226MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
227MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
228MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
229MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
230MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
231
232/* 16XX UART */
233MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
234MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
235MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
236MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
237MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
238MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
239
240/* I2C interface */
241MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
242MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
243
244/* Keypad */
245MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
246MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
247MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
248MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
249MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
250MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
251MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
252MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
253MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
254MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
255MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
256
257/* Power management */
258MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
259
260/* MCLK Settings */
261MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
262MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
263MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
264MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
265
266/* CompactFlash controller, conflicts with MMC1 */
267MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
268MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
269MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
270MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
271MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
272};
273#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
274
275int __init omap1_mux_init(void)
276{
277
278#ifdef CONFIG_ARCH_OMAP730
279 omap_mux_register(omap730_pins, ARRAY_SIZE(omap730_pins));
280#endif
281
282#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
283 omap_mux_register(omap1xxx_pins, ARRAY_SIZE(omap1xxx_pins));
284#endif
285
286 return 0;
287}
288
289#endif
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 40c4f7c40e73..6810cfb84462 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -109,9 +109,10 @@ static struct platform_device serial_device = {
109 * By default UART2 does not work on Innovator-1510 if you have 109 * By default UART2 does not work on Innovator-1510 if you have
110 * USB OHCI enabled. To use UART2, you must disable USB2 first. 110 * USB OHCI enabled. To use UART2, you must disable USB2 first.
111 */ 111 */
112void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS]) 112void __init omap_serial_init(void)
113{ 113{
114 int i; 114 int i;
115 const struct omap_uart_config *info;
115 116
116 if (cpu_is_omap730()) { 117 if (cpu_is_omap730()) {
117 serial_platform_data[0].regshift = 0; 118 serial_platform_data[0].regshift = 0;
@@ -126,10 +127,14 @@ void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
126 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16; 127 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
127 } 128 }
128 129
130 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
131 if (info == NULL)
132 return;
133
129 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { 134 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
130 unsigned char reg; 135 unsigned char reg;
131 136
132 if (ports[i] == 0) { 137 if (!((1 << i) & info->enabled_uarts)) {
133 serial_platform_data[i].membase = NULL; 138 serial_platform_data[i].membase = NULL;
134 serial_platform_data[i].mapbase = 0; 139 serial_platform_data[i].mapbase = 0;
135 continue; 140 continue;
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 191a9b1ee9b7..cdbf4d7620c6 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -226,8 +226,8 @@ unsigned long long sched_clock(void)
226 226
227#ifdef CONFIG_OMAP_32K_TIMER 227#ifdef CONFIG_OMAP_32K_TIMER
228 228
229#ifdef CONFIG_ARCH_OMAP1510 229#ifdef CONFIG_ARCH_OMAP15XX
230#error OMAP 32KHz timer does not currently work on 1510! 230#error OMAP 32KHz timer does not currently work on 15XX!
231#endif 231#endif
232 232
233/* 233/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 19:46:19 -0500