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authorTony Lindgren <tony@atomide.com>2008-01-25 03:42:48 -0500
committerTony Lindgren <tony@atomide.com>2008-04-14 12:57:11 -0400
commit225dfda1d676b70acf1e696ace68c23297926ce0 (patch)
tree4390425ac95cb0f4c62a2e042296df9e0b8c4eb6 /arch/arm/mach-omap1
parent7d7f665d5dac8d19f2fcb56baea09c59a3f861be (diff)
ARM: OMAP: Split omap_cfg_reg() into omap processor specific functions
Use omap processor specific function depending on system type. Based on an earlier patch by Klaus Pedersen <klaus.k.pedersen@nokia.com>. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap1')
-rw-r--r--arch/arm/mach-omap1/mux.c103
1 files changed, 103 insertions, 0 deletions
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index d74f6798d081..cf3bdc00cfdb 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -314,7 +314,110 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
314 314
315int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) 315int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
316{ 316{
317 static DEFINE_SPINLOCK(mux_spin_lock);
318 unsigned long flags;
319 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
320 pull_orig = 0, pull = 0;
321 unsigned int mask, warn = 0;
322
323 /* Check the mux register in question */
324 if (cfg->mux_reg) {
325 unsigned tmp1, tmp2;
326
327 spin_lock_irqsave(&mux_spin_lock, flags);
328 reg_orig = omap_readl(cfg->mux_reg);
329
330 /* The mux registers always seem to be 3 bits long */
331 mask = (0x7 << cfg->mask_offset);
332 tmp1 = reg_orig & mask;
333 reg = reg_orig & ~mask;
334
335 tmp2 = (cfg->mask << cfg->mask_offset);
336 reg |= tmp2;
337
338 if (tmp1 != tmp2)
339 warn = 1;
340
341 omap_writel(reg, cfg->mux_reg);
342 spin_unlock_irqrestore(&mux_spin_lock, flags);
343 }
344
345 /* Check for pull up or pull down selection on 1610 */
346 if (!cpu_is_omap15xx()) {
347 if (cfg->pu_pd_reg && cfg->pull_val) {
348 spin_lock_irqsave(&mux_spin_lock, flags);
349 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
350 mask = 1 << cfg->pull_bit;
351
352 if (cfg->pu_pd_val) {
353 if (!(pu_pd_orig & mask))
354 warn = 1;
355 /* Use pull up */
356 pu_pd = pu_pd_orig | mask;
357 } else {
358 if (pu_pd_orig & mask)
359 warn = 1;
360 /* Use pull down */
361 pu_pd = pu_pd_orig & ~mask;
362 }
363 omap_writel(pu_pd, cfg->pu_pd_reg);
364 spin_unlock_irqrestore(&mux_spin_lock, flags);
365 }
366 }
367
368 /* Check for an associated pull down register */
369 if (cfg->pull_reg) {
370 spin_lock_irqsave(&mux_spin_lock, flags);
371 pull_orig = omap_readl(cfg->pull_reg);
372 mask = 1 << cfg->pull_bit;
373
374 if (cfg->pull_val) {
375 if (pull_orig & mask)
376 warn = 1;
377 /* Low bit = pull enabled */
378 pull = pull_orig & ~mask;
379 } else {
380 if (!(pull_orig & mask))
381 warn = 1;
382 /* High bit = pull disabled */
383 pull = pull_orig | mask;
384 }
385
386 omap_writel(pull, cfg->pull_reg);
387 spin_unlock_irqrestore(&mux_spin_lock, flags);
388 }
389
390 if (warn) {
391#ifdef CONFIG_OMAP_MUX_WARNINGS
392 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
393#endif
394 }
395
396#ifdef CONFIG_OMAP_MUX_DEBUG
397 if (cfg->debug || warn) {
398 printk("MUX: Setting register %s\n", cfg->name);
399 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
400 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
401
402 if (!cpu_is_omap15xx()) {
403 if (cfg->pu_pd_reg && cfg->pull_val) {
404 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
405 cfg->pu_pd_name, cfg->pu_pd_reg,
406 pu_pd_orig, pu_pd);
407 }
408 }
409
410 if (cfg->pull_reg)
411 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
412 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
413 }
414#endif
415
416#ifdef CONFIG_OMAP_MUX_ERRORS
417 return warn ? -ETXTBSY : 0;
418#else
317 return 0; 419 return 0;
420#endif
318} 421}
319 422
320int __init omap1_mux_init(void) 423int __init omap1_mux_init(void)