Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (241 commits)
  [ARM] 5171/1: ep93xx: fix compilation of modules using clocks
  [ARM] 5133/2: at91sam9g20 defconfig file
  [ARM] 5130/4: Support for the at91sam9g20
  [ARM] 5160/1: IOP3XX: gpio/gpiolib support
  [ARM] at91: Fix NAND FLASH timings for at91sam9x evaluation kits.
  [ARM] 5084/1: zylonite: Register AC97 device
  [ARM] 5085/2: PXA: Move AC97 over to the new central device declaration model
  [ARM] 5120/1: pxa: correct platform driver names for PXA25x and PXA27x UDC drivers
  [ARM] 5147/1: pxaficp_ir: drop pxa_gpio_mode calls, as pin setting
  [ARM] 5145/1: PXA2xx: provide api to control IrDA pins state
  [ARM] 5144/1: pxaficp_ir: cleanup includes
  [ARM] pxa: remove pxa_set_cken()
  [ARM] pxa: allow clk aliases
  [ARM] Feroceon: don't disable BPU on boot
  [ARM] Orion: LED support for HP mv2120
  [ARM] Orion: add RD88F5181L-FXO support
  [ARM] Orion: add RD88F5181L-GE support
  [ARM] Orion: add Netgear WNR854T support
  [ARM] s3c2410_defconfig: update for current build
  [ARM] Acer n30: Minor style and indentation fixes.
  ...

1 files changed, 57 insertions, 0 deletions

diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
new file mode 100644
index 000000000000..126d252062d7
--- /dev/null
+++ b/arch/arm/mach-omap1/sram.S
@@ -0,0 +1,57 @@
+/*
+ * linux/arch/arm/plat-omap/sram-fn.S
+ *
+ * Functions that need to be run in internal SRAM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/arch/io.h>
+#include <asm/hardware.h>
+
+        .text
+
+/*
+ * Reprograms ULPD and CKCTL.
+ */
+ENTRY(omap1_sram_reprogram_clock)
+        stmfd   sp!, {r0 - r12, lr}             @ save registers on stack
+
+        mov     r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
+        orr     r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x00ff0000
+        orr     r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x0000ff00
+
+        mov     r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000
+        orr     r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
+        orr     r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
+
+        tst     r0, #1 << 4                     @ want lock mode?
+        beq     newck                           @ nope
+        bic     r0, r0, #1 << 4                 @ else clear lock bit
+        strh    r0, [r2]                        @ set dpll into bypass mode
+        orr     r0, r0, #1 << 4                 @ set lock bit again
+
+newck:
+        strh    r1, [r3]                        @ write new ckctl value
+        strh    r0, [r2]                        @ write new dpll value
+
+        mov     r4, #0x0700                     @ let the clocks settle
+        orr     r4, r4, #0x00ff
+delay:  sub     r4, r4, #1
+        cmp     r4, #0
+        bne     delay
+
+lock:   ldrh    r4, [r2], #0                    @ read back dpll value
+        tst     r0, #1 << 4                     @ want lock mode?
+        beq     out                             @ nope
+        tst     r4, #1 << 0                     @ dpll rate locked?
+        beq     lock                            @ try again
+
+out:
+        ldmfd   sp!, {r0 - r12, pc}             @ restore regs and return
+ENTRY(omap1_sram_reprogram_clock_sz)
+        .word   . - omap1_sram_reprogram_clock