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authorDavid S. Miller <davem@davemloft.net>2009-11-19 01:19:03 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-19 01:19:03 -0500
commit3505d1a9fd65e2d3e00827857b6795d9d8983658 (patch)
tree941cfafdb57c427bb6b7ebf6354ee93b2a3693b5 /arch/arm/mach-omap1/serial.c
parentdfef948ed2ba69cf041840b5e860d6b4e16fa0b1 (diff)
parent66b00a7c93ec782d118d2c03bd599cfd041e80a1 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts: drivers/net/sfc/sfe4001.c drivers/net/wireless/libertas/cmd.c drivers/staging/Kconfig drivers/staging/Makefile drivers/staging/rtl8187se/Kconfig drivers/staging/rtl8192e/Kconfig
Diffstat (limited to 'arch/arm/mach-omap1/serial.c')
-rw-r--r--arch/arm/mach-omap1/serial.c26
1 files changed, 0 insertions, 26 deletions
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index d496e50fec40..d23979bc0fd5 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -131,8 +131,6 @@ void __init omap_serial_init(void)
131 } 131 }
132 132
133 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { 133 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
134 unsigned char reg;
135
136 switch (i) { 134 switch (i) {
137 case 0: 135 case 0:
138 uart1_ck = clk_get(NULL, "uart1_ck"); 136 uart1_ck = clk_get(NULL, "uart1_ck");
@@ -143,16 +141,6 @@ void __init omap_serial_init(void)
143 if (cpu_is_omap15xx()) 141 if (cpu_is_omap15xx())
144 clk_set_rate(uart1_ck, 12000000); 142 clk_set_rate(uart1_ck, 12000000);
145 } 143 }
146 if (cpu_is_omap15xx()) {
147 omap_cfg_reg(UART1_TX);
148 omap_cfg_reg(UART1_RTS);
149 if (machine_is_omap_innovator()) {
150 reg = fpga_read(OMAP1510_FPGA_POWER);
151 reg |= OMAP1510_FPGA_PCR_COM1_EN;
152 fpga_write(reg, OMAP1510_FPGA_POWER);
153 udelay(10);
154 }
155 }
156 break; 144 break;
157 case 1: 145 case 1:
158 uart2_ck = clk_get(NULL, "uart2_ck"); 146 uart2_ck = clk_get(NULL, "uart2_ck");
@@ -165,16 +153,6 @@ void __init omap_serial_init(void)
165 else 153 else
166 clk_set_rate(uart2_ck, 48000000); 154 clk_set_rate(uart2_ck, 48000000);
167 } 155 }
168 if (cpu_is_omap15xx()) {
169 omap_cfg_reg(UART2_TX);
170 omap_cfg_reg(UART2_RTS);
171 if (machine_is_omap_innovator()) {
172 reg = fpga_read(OMAP1510_FPGA_POWER);
173 reg |= OMAP1510_FPGA_PCR_COM2_EN;
174 fpga_write(reg, OMAP1510_FPGA_POWER);
175 udelay(10);
176 }
177 }
178 break; 156 break;
179 case 2: 157 case 2:
180 uart3_ck = clk_get(NULL, "uart3_ck"); 158 uart3_ck = clk_get(NULL, "uart3_ck");
@@ -185,10 +163,6 @@ void __init omap_serial_init(void)
185 if (cpu_is_omap15xx()) 163 if (cpu_is_omap15xx())
186 clk_set_rate(uart3_ck, 12000000); 164 clk_set_rate(uart3_ck, 12000000);
187 } 165 }
188 if (cpu_is_omap15xx()) {
189 omap_cfg_reg(UART3_TX);
190 omap_cfg_reg(UART3_RX);
191 }
192 break; 166 break;
193 } 167 }
194 omap_serial_reset(&serial_platform_data[i]); 168 omap_serial_reset(&serial_platform_data[i]);