[PATCH] ARM: 2801/1: OMAP update 6/11: Split OMAP1 common code into id, io and serial

Patch from Tony Lindgren

This patch by Juha Yrjölä and other OMAP developers splits
OMAP1 specific common code into OMAP1 id, io, and serial
code in mach-omap1 directory.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 200 insertions, 0 deletions

diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
new file mode 100644
index 000000000000..214e5d17c8b5
--- /dev/null
+++ b/arch/arm/mach-omap1/serial.c
@@ -0,0 +1,200 @@
+/*
+ * linux/arch/arm/mach-omap1/id.c
+ *
+ * OMAP1 CPU identification code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_reg.h>
+
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/clock.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/fpga.h>
+
+static struct clk * uart1_ck = NULL;
+static struct clk * uart2_ck = NULL;
+static struct clk * uart3_ck = NULL;
+
+static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
+                                          int offset)
+{
+        offset <<= up->regshift;
+        return (unsigned int)__raw_readb(up->membase + offset);
+}
+
+static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
+                                    int value)
+{
+        offset <<= p->regshift;
+        __raw_writeb(value, p->membase + offset);
+}
+
+/*
+ * Internal UARTs need to be initialized for the 8250 autoconfig to work
+ * properly. Note that the TX watermark initialization may not be needed
+ * once the 8250.c watermark handling code is merged.
+ */
+static void __init omap_serial_reset(struct plat_serial8250_port *p)
+{
+        omap_serial_outp(p, UART_OMAP_MDR1, 0x07);      /* disable UART */
+        omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
+        omap_serial_outp(p, UART_OMAP_MDR1, 0x00);      /* enable UART */
+
+        if (!cpu_is_omap1510()) {
+                omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
+                while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
+        }
+}
+
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .membase        = (char*)IO_ADDRESS(OMAP_UART1_BASE),
+                .mapbase        = (unsigned long)OMAP_UART1_BASE,
+                .irq            = INT_UART1,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = OMAP16XX_BASE_BAUD * 16,
+        },
+        {
+                .membase        = (char*)IO_ADDRESS(OMAP_UART2_BASE),
+                .mapbase        = (unsigned long)OMAP_UART2_BASE,
+                .irq            = INT_UART2,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = OMAP16XX_BASE_BAUD * 16,
+        },
+        {
+                .membase        = (char*)IO_ADDRESS(OMAP_UART3_BASE),
+                .mapbase        = (unsigned long)OMAP_UART3_BASE,
+                .irq            = INT_UART3,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = OMAP16XX_BASE_BAUD * 16,
+        },
+        { },
+};
+
+static struct platform_device serial_device = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = serial_platform_data,
+        },
+};
+
+/*
+ * Note that on Innovator-1510 UART2 pins conflict with USB2.
+ * By default UART2 does not work on Innovator-1510 if you have
+ * USB OHCI enabled. To use UART2, you must disable USB2 first.
+ */
+void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
+{
+        int i;
+
+        if (cpu_is_omap730()) {
+                serial_platform_data[0].regshift = 0;
+                serial_platform_data[1].regshift = 0;
+                serial_platform_data[0].irq = INT_730_UART_MODEM_1;
+                serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
+        }
+
+        if (cpu_is_omap1510()) {
+                serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
+                serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
+                serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
+        }
+
+        for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+                unsigned char reg;
+
+                if (ports[i] == 0) {
+                        serial_platform_data[i].membase = NULL;
+                        serial_platform_data[i].mapbase = 0;
+                        continue;
+                }
+
+                switch (i) {
+                case 0:
+                        uart1_ck = clk_get(NULL, "uart1_ck");
+                        if (IS_ERR(uart1_ck))
+                                printk("Could not get uart1_ck\n");
+                        else {
+                                clk_use(uart1_ck);
+                                if (cpu_is_omap1510())
+                                        clk_set_rate(uart1_ck, 12000000);
+                        }
+                        if (cpu_is_omap1510()) {
+                                omap_cfg_reg(UART1_TX);
+                                omap_cfg_reg(UART1_RTS);
+                                if (machine_is_omap_innovator()) {
+                                        reg = fpga_read(OMAP1510_FPGA_POWER);
+                                        reg |= OMAP1510_FPGA_PCR_COM1_EN;
+                                        fpga_write(reg, OMAP1510_FPGA_POWER);
+                                        udelay(10);
+                                }
+                        }
+                        break;
+                case 1:
+                        uart2_ck = clk_get(NULL, "uart2_ck");
+                        if (IS_ERR(uart2_ck))
+                                printk("Could not get uart2_ck\n");
+                        else {
+                                clk_use(uart2_ck);
+                                if (cpu_is_omap1510())
+                                        clk_set_rate(uart2_ck, 12000000);
+                                else
+                                        clk_set_rate(uart2_ck, 48000000);
+                        }
+                        if (cpu_is_omap1510()) {
+                                omap_cfg_reg(UART2_TX);
+                                omap_cfg_reg(UART2_RTS);
+                                if (machine_is_omap_innovator()) {
+                                        reg = fpga_read(OMAP1510_FPGA_POWER);
+                                        reg |= OMAP1510_FPGA_PCR_COM2_EN;
+                                        fpga_write(reg, OMAP1510_FPGA_POWER);
+                                        udelay(10);
+                                }
+                        }
+                        break;
+                case 2:
+                        uart3_ck = clk_get(NULL, "uart3_ck");
+                        if (IS_ERR(uart3_ck))
+                                printk("Could not get uart3_ck\n");
+                        else {
+                                clk_use(uart3_ck);
+                                if (cpu_is_omap1510())
+                                        clk_set_rate(uart3_ck, 12000000);
+                        }
+                        if (cpu_is_omap1510()) {
+                                omap_cfg_reg(UART3_TX);
+                                omap_cfg_reg(UART3_RX);
+                        }
+                        break;
+                }
+                omap_serial_reset(&serial_platform_data[i]);
+        }
+}
+
+static int __init omap_init(void)
+{
+        return platform_device_register(&serial_device);
+}
+arch_initcall(omap_init);