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authorHiroshi DOYU <Hiroshi.DOYU@nokia.com>2006-12-07 18:43:59 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-05-09 05:37:10 -0400
commit340a614ac6766df18cba87ff7e66182193c2bd6d (patch)
treed1ad622625ba6933904567501a7387fc636c0a68 /arch/arm/mach-omap1/mailbox.c
parentc40fae9525e6c29c87a4f4361ff0a8d67a36e448 (diff)
ARM: OMAP: Add mailbox support for IVA
This patch adds a generic mailbox interface for for DSP and IVA (Image Video Accelerator). This patch itself doesn't contain any IVA driver. Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap1/mailbox.c')
-rw-r--r--arch/arm/mach-omap1/mailbox.c206
1 files changed, 206 insertions, 0 deletions
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
new file mode 100644
index 000000000000..d3abf5609902
--- /dev/null
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -0,0 +1,206 @@
1/*
2 * Mailbox reservation modules for DSP
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/kernel.h>
13#include <linux/resource.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <asm/arch/mailbox.h>
17#include <asm/arch/irqs.h>
18#include <asm/io.h>
19
20#define MAILBOX_ARM2DSP1 0x00
21#define MAILBOX_ARM2DSP1b 0x04
22#define MAILBOX_DSP2ARM1 0x08
23#define MAILBOX_DSP2ARM1b 0x0c
24#define MAILBOX_DSP2ARM2 0x10
25#define MAILBOX_DSP2ARM2b 0x14
26#define MAILBOX_ARM2DSP1_Flag 0x18
27#define MAILBOX_DSP2ARM1_Flag 0x1c
28#define MAILBOX_DSP2ARM2_Flag 0x20
29
30unsigned long mbox_base;
31
32struct omap_mbox1_fifo {
33 unsigned long cmd;
34 unsigned long data;
35 unsigned long flag;
36};
37
38struct omap_mbox1_priv {
39 struct omap_mbox1_fifo tx_fifo;
40 struct omap_mbox1_fifo rx_fifo;
41};
42
43static inline int mbox_read_reg(unsigned int reg)
44{
45 return __raw_readw(mbox_base + reg);
46}
47
48static inline void mbox_write_reg(unsigned int val, unsigned int reg)
49{
50 __raw_writew(val, mbox_base + reg);
51}
52
53/* msg */
54static inline mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
55{
56 struct omap_mbox1_fifo *fifo =
57 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
58 mbox_msg_t msg;
59
60 msg = mbox_read_reg(fifo->data);
61 msg |= ((mbox_msg_t) mbox_read_reg(fifo->cmd)) << 16;
62
63 return msg;
64}
65
66static inline void
67omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
68{
69 struct omap_mbox1_fifo *fifo =
70 &((struct omap_mbox1_priv *)mbox->priv)->tx_fifo;
71
72 mbox_write_reg(msg & 0xffff, fifo->data);
73 mbox_write_reg(msg >> 16, fifo->cmd);
74}
75
76static inline int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
77{
78 return 0;
79}
80
81static inline int omap1_mbox_fifo_full(struct omap_mbox *mbox)
82{
83 struct omap_mbox1_fifo *fifo =
84 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
85
86 return (mbox_read_reg(fifo->flag));
87}
88
89/* irq */
90static inline void
91omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
92{
93 if (irq == IRQ_RX)
94 enable_irq(mbox->irq);
95}
96
97static inline void
98omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
99{
100 if (irq == IRQ_RX)
101 disable_irq(mbox->irq);
102}
103
104static inline int
105omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
106{
107 if (irq == IRQ_TX)
108 return 0;
109 return 1;
110}
111
112static struct omap_mbox_ops omap1_mbox_ops = {
113 .type = OMAP_MBOX_TYPE1,
114 .fifo_read = omap1_mbox_fifo_read,
115 .fifo_write = omap1_mbox_fifo_write,
116 .fifo_empty = omap1_mbox_fifo_empty,
117 .fifo_full = omap1_mbox_fifo_full,
118 .enable_irq = omap1_mbox_enable_irq,
119 .disable_irq = omap1_mbox_disable_irq,
120 .is_irq = omap1_mbox_is_irq,
121};
122
123/* FIXME: the following struct should be created automatically by the user id */
124
125/* DSP */
126static struct omap_mbox1_priv omap1_mbox_dsp_priv = {
127 .tx_fifo = {
128 .cmd = MAILBOX_ARM2DSP1b,
129 .data = MAILBOX_ARM2DSP1,
130 .flag = MAILBOX_ARM2DSP1_Flag,
131 },
132 .rx_fifo = {
133 .cmd = MAILBOX_DSP2ARM1b,
134 .data = MAILBOX_DSP2ARM1,
135 .flag = MAILBOX_DSP2ARM1_Flag,
136 },
137};
138
139struct omap_mbox mbox_dsp_info = {
140 .name = "dsp",
141 .ops = &omap1_mbox_ops,
142 .priv = &omap1_mbox_dsp_priv,
143};
144EXPORT_SYMBOL(mbox_dsp_info);
145
146static int __init omap1_mbox_probe(struct platform_device *pdev)
147{
148 struct resource *res;
149 int ret = 0;
150
151 if (pdev->num_resources != 2) {
152 dev_err(&pdev->dev, "invalid number of resources: %d\n",
153 pdev->num_resources);
154 return -ENODEV;
155 }
156
157 /* MBOX base */
158 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
159 if (unlikely(!res)) {
160 dev_err(&pdev->dev, "invalid mem resource\n");
161 return -ENODEV;
162 }
163 mbox_base = res->start;
164
165 /* DSP IRQ */
166 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
167 if (unlikely(!res)) {
168 dev_err(&pdev->dev, "invalid irq resource\n");
169 return -ENODEV;
170 }
171 mbox_dsp_info.irq = res->start;
172
173 ret = omap_mbox_register(&mbox_dsp_info);
174
175 return ret;
176}
177
178static int omap1_mbox_remove(struct platform_device *pdev)
179{
180 omap_mbox_unregister(&mbox_dsp_info);
181
182 return 0;
183}
184
185static struct platform_driver omap1_mbox_driver = {
186 .probe = omap1_mbox_probe,
187 .remove = omap1_mbox_remove,
188 .driver = {
189 .name = "mailbox",
190 },
191};
192
193static int __init omap1_mbox_init(void)
194{
195 return platform_driver_register(&omap1_mbox_driver);
196}
197
198static void __exit omap1_mbox_exit(void)
199{
200 platform_driver_unregister(&omap1_mbox_driver);
201}
202
203module_init(omap1_mbox_init);
204module_exit(omap1_mbox_exit);
205
206MODULE_LICENSE("GPL");