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author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-15 15:33:40 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-15 15:33:40 -0500 |
commit | 16c1020362083b320868c0deef492249089c3cd3 (patch) | |
tree | ff200df3502e6010745713275d69fd0a07e399cf /arch/arm/mach-omap1/irq.c | |
parent | 65e5d002b5ad220db2bf9557f53de5a98f7dab86 (diff) | |
parent | bbba75606963c82febf7bd2761ea848ac5d1a1bb (diff) |
Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (161 commits)
ARM: pxa: fix building issue of missing physmap.h
ARM: mmp: PXA910 drive strength FAST using wrong value
ARM: mmp: MMP2 drive strength FAST using wrong value
ARM: pxa: fix recursive calls in pxa_low_gpio_chip
AT91: Support for gsia18s board
AT91: Acme Systems FOX Board G20 board files
AT91: board-sam9m10g45ek.c: Remove duplicate inclusion of mach/hardware.h
ARM: pxa: fix suspend/resume array index miscalculation
ARM: pxa: use cpu_has_ipr() consistently in irq.c
ARM: pxa: remove unused variable in clock-pxa3xx.c
ARM: pxa: fix warning in zeus.c
ARM: sa1111: fix typo in sa1111_retrigger_lowirq()
ARM mxs: clkdev related compile fixes
ARM i.MX mx31_3ds: Fix MC13783 regulator names
ARM: plat-stmp3xxx: irq_data conversion.
ARM: plat-spear: irq_data conversion.
ARM: plat-orion: irq_data conversion.
ARM: plat-omap: irq_data conversion.
ARM: plat-nomadik: irq_data conversion.
ARM: plat-mxc: irq_data conversion.
...
Fix up trivial conflict in arch/arm/plat-omap/gpio.c (Lennert
Buytenhek's irq_data conversion clashing with some omap irq updates)
Diffstat (limited to 'arch/arm/mach-omap1/irq.c')
-rw-r--r-- | arch/arm/mach-omap1/irq.c | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 6bddbc869f4c..47701584df35 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c | |||
@@ -70,48 +70,48 @@ static inline void irq_bank_writel(unsigned long value, int bank, int offset) | |||
70 | omap_writel(value, irq_banks[bank].base_reg + offset); | 70 | omap_writel(value, irq_banks[bank].base_reg + offset); |
71 | } | 71 | } |
72 | 72 | ||
73 | static void omap_ack_irq(unsigned int irq) | 73 | static void omap_ack_irq(struct irq_data *d) |
74 | { | 74 | { |
75 | if (irq > 31) | 75 | if (d->irq > 31) |
76 | omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET); | 76 | omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET); |
77 | 77 | ||
78 | omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET); | 78 | omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET); |
79 | } | 79 | } |
80 | 80 | ||
81 | static void omap_mask_irq(unsigned int irq) | 81 | static void omap_mask_irq(struct irq_data *d) |
82 | { | 82 | { |
83 | int bank = IRQ_BANK(irq); | 83 | int bank = IRQ_BANK(d->irq); |
84 | u32 l; | 84 | u32 l; |
85 | 85 | ||
86 | l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); | 86 | l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); |
87 | l |= 1 << IRQ_BIT(irq); | 87 | l |= 1 << IRQ_BIT(d->irq); |
88 | omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); | 88 | omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); |
89 | } | 89 | } |
90 | 90 | ||
91 | static void omap_unmask_irq(unsigned int irq) | 91 | static void omap_unmask_irq(struct irq_data *d) |
92 | { | 92 | { |
93 | int bank = IRQ_BANK(irq); | 93 | int bank = IRQ_BANK(d->irq); |
94 | u32 l; | 94 | u32 l; |
95 | 95 | ||
96 | l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); | 96 | l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); |
97 | l &= ~(1 << IRQ_BIT(irq)); | 97 | l &= ~(1 << IRQ_BIT(d->irq)); |
98 | omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); | 98 | omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); |
99 | } | 99 | } |
100 | 100 | ||
101 | static void omap_mask_ack_irq(unsigned int irq) | 101 | static void omap_mask_ack_irq(struct irq_data *d) |
102 | { | 102 | { |
103 | omap_mask_irq(irq); | 103 | omap_mask_irq(d); |
104 | omap_ack_irq(irq); | 104 | omap_ack_irq(d); |
105 | } | 105 | } |
106 | 106 | ||
107 | static int omap_wake_irq(unsigned int irq, unsigned int enable) | 107 | static int omap_wake_irq(struct irq_data *d, unsigned int enable) |
108 | { | 108 | { |
109 | int bank = IRQ_BANK(irq); | 109 | int bank = IRQ_BANK(d->irq); |
110 | 110 | ||
111 | if (enable) | 111 | if (enable) |
112 | irq_banks[bank].wake_enable |= IRQ_BIT(irq); | 112 | irq_banks[bank].wake_enable |= IRQ_BIT(d->irq); |
113 | else | 113 | else |
114 | irq_banks[bank].wake_enable &= ~IRQ_BIT(irq); | 114 | irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq); |
115 | 115 | ||
116 | return 0; | 116 | return 0; |
117 | } | 117 | } |
@@ -168,10 +168,10 @@ static struct omap_irq_bank omap1610_irq_banks[] = { | |||
168 | 168 | ||
169 | static struct irq_chip omap_irq_chip = { | 169 | static struct irq_chip omap_irq_chip = { |
170 | .name = "MPU", | 170 | .name = "MPU", |
171 | .ack = omap_mask_ack_irq, | 171 | .irq_ack = omap_mask_ack_irq, |
172 | .mask = omap_mask_irq, | 172 | .irq_mask = omap_mask_irq, |
173 | .unmask = omap_unmask_irq, | 173 | .irq_unmask = omap_unmask_irq, |
174 | .set_wake = omap_wake_irq, | 174 | .irq_set_wake = omap_wake_irq, |
175 | }; | 175 | }; |
176 | 176 | ||
177 | void __init omap_init_irq(void) | 177 | void __init omap_init_irq(void) |
@@ -239,9 +239,9 @@ void __init omap_init_irq(void) | |||
239 | /* Unmask level 2 handler */ | 239 | /* Unmask level 2 handler */ |
240 | 240 | ||
241 | if (cpu_is_omap7xx()) | 241 | if (cpu_is_omap7xx()) |
242 | omap_unmask_irq(INT_7XX_IH2_IRQ); | 242 | omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ)); |
243 | else if (cpu_is_omap15xx()) | 243 | else if (cpu_is_omap15xx()) |
244 | omap_unmask_irq(INT_1510_IH2_IRQ); | 244 | omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ)); |
245 | else if (cpu_is_omap16xx()) | 245 | else if (cpu_is_omap16xx()) |
246 | omap_unmask_irq(INT_1610_IH2_IRQ); | 246 | omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ)); |
247 | } | 247 | } |