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authorLinus Torvalds <torvalds@g5.osdl.org>2006-04-02 16:34:00 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-04-02 16:34:00 -0400
commit1810b6cb162e0c19e0ecbbacbcfd66f578f335ec (patch)
tree810494ca945483bf669a062d445d49d3bfb7d6a7 /arch/arm/mach-omap1/irq.c
parentef7a4567dc542d8cc563755478464ea928fede41 (diff)
parent9b6553cd01ce3ea7a6a532f7b7e62e3535d6b102 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (27 commits) [ARM] 3433/1: ARM: OMAP: 8/8 Update board files [ARM] 3455/1: ARM: OMAP: 7/8 Misc updates, take 2 [ARM] 3454/1: ARM: OMAP: 6/8 Update framebuffer low-level init code, take 2 [ARM] 3430/1: ARM: OMAP: 5/8 Update PM [ARM] 3429/1: ARM: OMAP: 4/8 Update GPIO [ARM] 3428/1: ARM: OMAP: 3/8 Update pin multiplexing [ARM] 3427/1: ARM: OMAP: 2/8 Update timers [ARM] 3426/1: ARM: OMAP: 1/8 Update clock framework [ARM] 3396/2: AT91RM9200 Platform devices update [ARM] 3395/2: AT91RM9200 Dataflash Card vs MMC selection [ARM] 3393/2: AT91RM9200 LED support [ARM] 3453/1: Poodle: Correctly set the memory size [ARM] 3446/1: i.MX: MMC/SD SDHC controller registration for i.MX/MX1 MX1ADS board [ARM] 3444/1: i.MX: Scatter-gather DMA emulation for i.MX/MX1 [ARM] 3451/1: ep93xx: use the m48t86 rtc driver on the ts72xx platform [ARM] 3450/1: ep93xx: use the ep93xx rtc driver [ARM] 3452/1: [S3C2410] RX3715 - add nand information [ARM] 3449/1: [S3C2410] Anubis - fix NAND timings [ARM] 3448/1: [S3C2410] Settle delay when _enabling_ USB PLL [ARM] 3442/1: [S3C2410] SMDK: NAND device setup ...
Diffstat (limited to 'arch/arm/mach-omap1/irq.c')
-rw-r--r--arch/arm/mach-omap1/irq.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index ed65a7d2e941..a0431c00fa81 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -60,7 +60,7 @@ struct omap_irq_bank {
60 unsigned long wake_enable; 60 unsigned long wake_enable;
61}; 61};
62 62
63static unsigned int irq_bank_count = 0; 63static unsigned int irq_bank_count;
64static struct omap_irq_bank *irq_banks; 64static struct omap_irq_bank *irq_banks;
65 65
66static inline unsigned int irq_bank_readl(int bank, int offset) 66static inline unsigned int irq_bank_readl(int bank, int offset)
@@ -142,28 +142,28 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
142 142
143#ifdef CONFIG_ARCH_OMAP730 143#ifdef CONFIG_ARCH_OMAP730
144static struct omap_irq_bank omap730_irq_banks[] = { 144static struct omap_irq_bank omap730_irq_banks[] = {
145 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, 145 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
146 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, 146 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
147 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, 147 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
148}; 148};
149#endif 149#endif
150 150
151#ifdef CONFIG_ARCH_OMAP15XX 151#ifdef CONFIG_ARCH_OMAP15XX
152static struct omap_irq_bank omap1510_irq_banks[] = { 152static struct omap_irq_bank omap1510_irq_banks[] = {
153 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, 153 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
154 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, 154 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
155}; 155};
156static struct omap_irq_bank omap310_irq_banks[] = { 156static struct omap_irq_bank omap310_irq_banks[] = {
157 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 }, 157 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
158 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 }, 158 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
159}; 159};
160#endif 160#endif
161 161
162#if defined(CONFIG_ARCH_OMAP16XX) 162#if defined(CONFIG_ARCH_OMAP16XX)
163 163
164static struct omap_irq_bank omap1610_irq_banks[] = { 164static struct omap_irq_bank omap1610_irq_banks[] = {
165 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, 165 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
166 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, 166 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
167 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, 167 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
168 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, 168 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
169}; 169};