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authorTony Lindgren <tony@atomide.com>2012-09-12 23:42:36 -0400
committerTony Lindgren <tony@atomide.com>2012-09-12 23:42:36 -0400
commit3c101c41fbe5daf88afbbd575542aa1d047812bb (patch)
tree97b8837a7ef888f07d01ff7109303402dd8fed2e /arch/arm/mach-omap1/clock_data.c
parentf191f40c1819ffdca05408e6349f7fd30ef1cc36 (diff)
parent7852ec0536ca39cefffc6301dc77f8ae55592926 (diff)
Merge tag 'omap-cleanup-b-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into cleanup-makefile-sparse
smatch and string-wrapping cleanups for the OMAP subarch code. These changes fix some of the more meaningful warnings that smatch returns for the OMAP subarch code, and unwraps strings that are wrapped at the 80-column boundary, to conform with the current practice. Basic build, boot, and PM logs are available here: http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/
Diffstat (limited to 'arch/arm/mach-omap1/clock_data.c')
-rw-r--r--arch/arm/mach-omap1/clock_data.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 6a32b9b0dc30..9b45f4b0ee22 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -775,11 +775,10 @@ static struct clk_functions omap1_clk_functions = {
775 775
776static void __init omap1_show_rates(void) 776static void __init omap1_show_rates(void)
777{ 777{
778 pr_notice("Clocking rate (xtal/DPLL1/MPU): " 778 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
779 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", 779 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
780 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, 780 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
781 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, 781 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
782 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
783} 782}
784 783
785u32 cpu_mask; 784u32 cpu_mask;
@@ -840,8 +839,8 @@ int __init omap1_clk_init(void)
840 if (cpu_is_omap16xx() && crystal_type == 2) 839 if (cpu_is_omap16xx() && crystal_type == 2)
841 ck_ref.rate = 19200000; 840 ck_ref.rate = 19200000;
842 841
843 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " 842 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
844 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), 843 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
845 omap_readw(ARM_CKCTL)); 844 omap_readw(ARM_CKCTL));
846 845
847 /* We want to be in syncronous scalable mode */ 846 /* We want to be in syncronous scalable mode */