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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-11-04 11:35:03 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 06:38:39 -0500
commit897dcded6fb6565f4d1c22a55d21f135403db132 (patch)
treeda9c4028ed49a1482445131760b4fc45c6524abe /arch/arm/mach-omap1/clock.h
parent548d849574847b788fe846fe21a41386063be161 (diff)
[ARM] omap: provide a NULL clock operations structure
... and use it for clocks which are ALWAYS_ENABLED. These clocks use a non-NULL enable_reg pointer for other purposes (such as selecting clock rates.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap1/clock.h')
-rw-r--r--arch/arm/mach-omap1/clock.h78
1 files changed, 36 insertions, 42 deletions
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 5b93a2a897ad..8673832d829a 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -144,18 +144,18 @@ static struct mpu_rate rate_table[] = {
144 144
145static struct clk ck_ref = { 145static struct clk ck_ref = {
146 .name = "ck_ref", 146 .name = "ck_ref",
147 .ops = &clkops_generic, 147 .ops = &clkops_null,
148 .rate = 12000000, 148 .rate = 12000000,
149 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 149 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
150 CLOCK_IN_OMAP310 | ALWAYS_ENABLED, 150 CLOCK_IN_OMAP310,
151}; 151};
152 152
153static struct clk ck_dpll1 = { 153static struct clk ck_dpll1 = {
154 .name = "ck_dpll1", 154 .name = "ck_dpll1",
155 .ops = &clkops_generic, 155 .ops = &clkops_null,
156 .parent = &ck_ref, 156 .parent = &ck_ref,
157 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 157 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
158 CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED, 158 CLOCK_IN_OMAP310 | RATE_PROPAGATES,
159}; 159};
160 160
161static struct arm_idlect1_clk ck_dpll1out = { 161static struct arm_idlect1_clk ck_dpll1out = {
@@ -186,11 +186,10 @@ static struct clk sossi_ck = {
186 186
187static struct clk arm_ck = { 187static struct clk arm_ck = {
188 .name = "arm_ck", 188 .name = "arm_ck",
189 .ops = &clkops_generic, 189 .ops = &clkops_null,
190 .parent = &ck_dpll1, 190 .parent = &ck_dpll1,
191 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 191 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
192 CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES | 192 CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES,
193 ALWAYS_ENABLED,
194 .rate_offset = CKCTL_ARMDIV_OFFSET, 193 .rate_offset = CKCTL_ARMDIV_OFFSET,
195 .recalc = &omap1_ckctl_recalc, 194 .recalc = &omap1_ckctl_recalc,
196}; 195};
@@ -265,9 +264,9 @@ static struct arm_idlect1_clk armwdt_ck = {
265 264
266static struct clk arminth_ck16xx = { 265static struct clk arminth_ck16xx = {
267 .name = "arminth_ck", 266 .name = "arminth_ck",
268 .ops = &clkops_generic, 267 .ops = &clkops_null,
269 .parent = &arm_ck, 268 .parent = &arm_ck,
270 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 269 .flags = CLOCK_IN_OMAP16XX,
271 .recalc = &followparent_recalc, 270 .recalc = &followparent_recalc,
272 /* Note: On 16xx the frequency can be divided by 2 by programming 271 /* Note: On 16xx the frequency can be divided by 2 by programming
273 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 272 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
@@ -290,10 +289,10 @@ static struct clk dsp_ck = {
290 289
291static struct clk dspmmu_ck = { 290static struct clk dspmmu_ck = {
292 .name = "dspmmu_ck", 291 .name = "dspmmu_ck",
293 .ops = &clkops_generic, 292 .ops = &clkops_null,
294 .parent = &ck_dpll1, 293 .parent = &ck_dpll1,
295 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 294 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
296 RATE_CKCTL | ALWAYS_ENABLED, 295 RATE_CKCTL,
297 .rate_offset = CKCTL_DSPMMUDIV_OFFSET, 296 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
298 .recalc = &omap1_ckctl_recalc, 297 .recalc = &omap1_ckctl_recalc,
299}; 298};
@@ -337,12 +336,12 @@ static struct clk dsptim_ck = {
337static struct arm_idlect1_clk tc_ck = { 336static struct arm_idlect1_clk tc_ck = {
338 .clk = { 337 .clk = {
339 .name = "tc_ck", 338 .name = "tc_ck",
340 .ops = &clkops_generic, 339 .ops = &clkops_null,
341 .parent = &ck_dpll1, 340 .parent = &ck_dpll1,
342 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 341 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
343 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | 342 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
344 RATE_CKCTL | RATE_PROPAGATES | 343 RATE_CKCTL | RATE_PROPAGATES |
345 ALWAYS_ENABLED | CLOCK_IDLE_CONTROL, 344 CLOCK_IDLE_CONTROL,
346 .rate_offset = CKCTL_TCDIV_OFFSET, 345 .rate_offset = CKCTL_TCDIV_OFFSET,
347 .recalc = &omap1_ckctl_recalc, 346 .recalc = &omap1_ckctl_recalc,
348 }, 347 },
@@ -351,10 +350,9 @@ static struct arm_idlect1_clk tc_ck = {
351 350
352static struct clk arminth_ck1510 = { 351static struct clk arminth_ck1510 = {
353 .name = "arminth_ck", 352 .name = "arminth_ck",
354 .ops = &clkops_generic, 353 .ops = &clkops_null,
355 .parent = &tc_ck.clk, 354 .parent = &tc_ck.clk,
356 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 355 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
357 ALWAYS_ENABLED,
358 .recalc = &followparent_recalc, 356 .recalc = &followparent_recalc,
359 /* Note: On 1510 the frequency follows TC_CK 357 /* Note: On 1510 the frequency follows TC_CK
360 * 358 *
@@ -365,10 +363,9 @@ static struct clk arminth_ck1510 = {
365static struct clk tipb_ck = { 363static struct clk tipb_ck = {
366 /* No-idle controlled by "tc_ck" */ 364 /* No-idle controlled by "tc_ck" */
367 .name = "tipb_ck", 365 .name = "tipb_ck",
368 .ops = &clkops_generic, 366 .ops = &clkops_null,
369 .parent = &tc_ck.clk, 367 .parent = &tc_ck.clk,
370 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 368 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
371 ALWAYS_ENABLED,
372 .recalc = &followparent_recalc, 369 .recalc = &followparent_recalc,
373}; 370};
374 371
@@ -406,18 +403,18 @@ static struct clk tc2_ck = {
406static struct clk dma_ck = { 403static struct clk dma_ck = {
407 /* No-idle controlled by "tc_ck" */ 404 /* No-idle controlled by "tc_ck" */
408 .name = "dma_ck", 405 .name = "dma_ck",
409 .ops = &clkops_generic, 406 .ops = &clkops_null,
410 .parent = &tc_ck.clk, 407 .parent = &tc_ck.clk,
411 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 408 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
412 CLOCK_IN_OMAP310 | ALWAYS_ENABLED, 409 CLOCK_IN_OMAP310,
413 .recalc = &followparent_recalc, 410 .recalc = &followparent_recalc,
414}; 411};
415 412
416static struct clk dma_lcdfree_ck = { 413static struct clk dma_lcdfree_ck = {
417 .name = "dma_lcdfree_ck", 414 .name = "dma_lcdfree_ck",
418 .ops = &clkops_generic, 415 .ops = &clkops_null,
419 .parent = &tc_ck.clk, 416 .parent = &tc_ck.clk,
420 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 417 .flags = CLOCK_IN_OMAP16XX,
421 .recalc = &followparent_recalc, 418 .recalc = &followparent_recalc,
422}; 419};
423 420
@@ -451,17 +448,17 @@ static struct arm_idlect1_clk lb_ck = {
451 448
452static struct clk rhea1_ck = { 449static struct clk rhea1_ck = {
453 .name = "rhea1_ck", 450 .name = "rhea1_ck",
454 .ops = &clkops_generic, 451 .ops = &clkops_null,
455 .parent = &tc_ck.clk, 452 .parent = &tc_ck.clk,
456 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 453 .flags = CLOCK_IN_OMAP16XX,
457 .recalc = &followparent_recalc, 454 .recalc = &followparent_recalc,
458}; 455};
459 456
460static struct clk rhea2_ck = { 457static struct clk rhea2_ck = {
461 .name = "rhea2_ck", 458 .name = "rhea2_ck",
462 .ops = &clkops_generic, 459 .ops = &clkops_null,
463 .parent = &tc_ck.clk, 460 .parent = &tc_ck.clk,
464 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, 461 .flags = CLOCK_IN_OMAP16XX,
465 .recalc = &followparent_recalc, 462 .recalc = &followparent_recalc,
466}; 463};
467 464
@@ -493,13 +490,12 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
493 490
494static struct clk uart1_1510 = { 491static struct clk uart1_1510 = {
495 .name = "uart1_ck", 492 .name = "uart1_ck",
496 .ops = &clkops_generic, 493 .ops = &clkops_null,
497 /* Direct from ULPD, no real parent */ 494 /* Direct from ULPD, no real parent */
498 .parent = &armper_ck.clk, 495 .parent = &armper_ck.clk,
499 .rate = 12000000, 496 .rate = 12000000,
500 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 497 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
501 ENABLE_REG_32BIT | ALWAYS_ENABLED | 498 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
502 CLOCK_NO_IDLE_PARENT,
503 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 499 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
504 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ 500 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
505 .set_rate = &omap1_set_uart_rate, 501 .set_rate = &omap1_set_uart_rate,
@@ -523,13 +519,13 @@ static struct uart_clk uart1_16xx = {
523 519
524static struct clk uart2_ck = { 520static struct clk uart2_ck = {
525 .name = "uart2_ck", 521 .name = "uart2_ck",
526 .ops = &clkops_generic, 522 .ops = &clkops_null,
527 /* Direct from ULPD, no real parent */ 523 /* Direct from ULPD, no real parent */
528 .parent = &armper_ck.clk, 524 .parent = &armper_ck.clk,
529 .rate = 12000000, 525 .rate = 12000000,
530 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 526 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
531 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | 527 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
532 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, 528 CLOCK_NO_IDLE_PARENT,
533 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 529 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
534 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ 530 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
535 .set_rate = &omap1_set_uart_rate, 531 .set_rate = &omap1_set_uart_rate,
@@ -538,13 +534,12 @@ static struct clk uart2_ck = {
538 534
539static struct clk uart3_1510 = { 535static struct clk uart3_1510 = {
540 .name = "uart3_ck", 536 .name = "uart3_ck",
541 .ops = &clkops_generic, 537 .ops = &clkops_null,
542 /* Direct from ULPD, no real parent */ 538 /* Direct from ULPD, no real parent */
543 .parent = &armper_ck.clk, 539 .parent = &armper_ck.clk,
544 .rate = 12000000, 540 .rate = 12000000,
545 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 541 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
546 ENABLE_REG_32BIT | ALWAYS_ENABLED | 542 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
547 CLOCK_NO_IDLE_PARENT,
548 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 543 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
549 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ 544 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
550 .set_rate = &omap1_set_uart_rate, 545 .set_rate = &omap1_set_uart_rate,
@@ -680,9 +675,9 @@ static struct clk mmc2_ck = {
680 675
681static struct clk virtual_ck_mpu = { 676static struct clk virtual_ck_mpu = {
682 .name = "mpu", 677 .name = "mpu",
683 .ops = &clkops_generic, 678 .ops = &clkops_null,
684 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 679 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
685 CLOCK_IN_OMAP310 | ALWAYS_ENABLED, 680 CLOCK_IN_OMAP310,
686 .parent = &arm_ck, /* Is smarter alias for */ 681 .parent = &arm_ck, /* Is smarter alias for */
687 .recalc = &followparent_recalc, 682 .recalc = &followparent_recalc,
688 .set_rate = &omap1_select_table_rate, 683 .set_rate = &omap1_select_table_rate,
@@ -694,9 +689,9 @@ remains active during MPU idle whenever this is enabled */
694static struct clk i2c_fck = { 689static struct clk i2c_fck = {
695 .name = "i2c_fck", 690 .name = "i2c_fck",
696 .id = 1, 691 .id = 1,
697 .ops = &clkops_generic, 692 .ops = &clkops_null,
698 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 693 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
699 CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED, 694 CLOCK_NO_IDLE_PARENT,
700 .parent = &armxor_ck.clk, 695 .parent = &armxor_ck.clk,
701 .recalc = &followparent_recalc, 696 .recalc = &followparent_recalc,
702}; 697};
@@ -704,9 +699,8 @@ static struct clk i2c_fck = {
704static struct clk i2c_ick = { 699static struct clk i2c_ick = {
705 .name = "i2c_ick", 700 .name = "i2c_ick",
706 .id = 1, 701 .id = 1,
707 .ops = &clkops_generic, 702 .ops = &clkops_null,
708 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | 703 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT,
709 ALWAYS_ENABLED,
710 .parent = &armper_ck.clk, 704 .parent = &armper_ck.clk,
711 .recalc = &followparent_recalc, 705 .recalc = &followparent_recalc,
712}; 706};