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authorLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
commita8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch)
tree887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/mach-omap1/clock.c
parent168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff)
parent2dc7667b9d0674db6572723356fe3857031101a4 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
Diffstat (limited to 'arch/arm/mach-omap1/clock.c')
-rw-r--r--arch/arm/mach-omap1/clock.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 619db18144ea..f1958e882e86 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1,3 +1,4 @@
1//kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
1/* 2/*
2 * linux/arch/arm/mach-omap1/clock.c 3 * linux/arch/arm/mach-omap1/clock.c
3 * 4 *
@@ -20,6 +21,7 @@
20 21
21#include <asm/io.h> 22#include <asm/io.h>
22 23
24#include <asm/arch/cpu.h>
23#include <asm/arch/usb.h> 25#include <asm/arch/usb.h>
24#include <asm/arch/clock.h> 26#include <asm/arch/clock.h>
25#include <asm/arch/sram.h> 27#include <asm/arch/sram.h>
@@ -270,8 +272,12 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
270 /* 272 /*
271 * In most cases we should not need to reprogram DPLL. 273 * In most cases we should not need to reprogram DPLL.
272 * Reprogramming the DPLL is tricky, it must be done from SRAM. 274 * Reprogramming the DPLL is tricky, it must be done from SRAM.
275 * (on 730, bit 13 must always be 1)
273 */ 276 */
274 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 277 if (cpu_is_omap730())
278 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
279 else
280 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
275 281
276 ck_dpll1.rate = ptr->pll_rate; 282 ck_dpll1.rate = ptr->pll_rate;
277 propagate_rate(&ck_dpll1); 283 propagate_rate(&ck_dpll1);
@@ -748,7 +754,7 @@ int __init omap1_clk_init(void)
748 printk(KERN_ERR "System frequencies not set. Check your config.\n"); 754 printk(KERN_ERR "System frequencies not set. Check your config.\n");
749 /* Guess sane values (60MHz) */ 755 /* Guess sane values (60MHz) */
750 omap_writew(0x2290, DPLL_CTL); 756 omap_writew(0x2290, DPLL_CTL);
751 omap_writew(0x1005, ARM_CKCTL); 757 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
752 ck_dpll1.rate = 60000000; 758 ck_dpll1.rate = 60000000;
753 propagate_rate(&ck_dpll1); 759 propagate_rate(&ck_dpll1);
754 } 760 }
@@ -761,13 +767,17 @@ int __init omap1_clk_init(void)
761 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, 767 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
762 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); 768 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
763 769
764#ifdef CONFIG_MACH_OMAP_PERSEUS2 770#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
765 /* Select slicer output as OMAP input clock */ 771 /* Select slicer output as OMAP input clock */
766 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); 772 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
767#endif 773#endif
768 774
769 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 775 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
770 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); 776 /* (on 730, bit 13 must not be cleared) */
777 if (cpu_is_omap730())
778 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
779 else
780 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
771 781
772 /* Put DSP/MPUI into reset until needed */ 782 /* Put DSP/MPUI into reset until needed */
773 omap_writew(0, ARM_RSTCT1); 783 omap_writew(0, ARM_RSTCT1);