diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-11-13 08:07:00 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-08 12:50:10 -0500 |
commit | a9e882096317a088087b608d272da7029a6cc8c8 (patch) | |
tree | f7b022e917f163b76aef43c259e8ca25eb4a50d8 /arch/arm/mach-omap1/clock.c | |
parent | c6af45085211db8720d6b94b3985ce7198d764e3 (diff) |
[ARM] omap: remove unnecessary calls to propagate_rate()
We've always called propagate_rate() in the parent function to
the .set_rate methods, so there's no point having the .set_rate
methods also call this heavy-weight function - it's mere
duplication of what's happening elsewhere.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap1/clock.c')
-rw-r--r-- | arch/arm/mach-omap1/clock.c | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index ee1b9f20544a..80a58e9dbba3 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
@@ -308,7 +308,6 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | |||
308 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); | 308 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); |
309 | 309 | ||
310 | ck_dpll1.rate = ptr->pll_rate; | 310 | ck_dpll1.rate = ptr->pll_rate; |
311 | propagate_rate(&ck_dpll1); | ||
312 | return 0; | 311 | return 0; |
313 | } | 312 | } |
314 | 313 | ||
@@ -333,9 +332,6 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) | |||
333 | ret = 0; | 332 | ret = 0; |
334 | } | 333 | } |
335 | 334 | ||
336 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | ||
337 | propagate_rate(clk); | ||
338 | |||
339 | return ret; | 335 | return ret; |
340 | } | 336 | } |
341 | 337 | ||
@@ -442,8 +438,6 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) | |||
442 | omap_writel(l, MOD_CONF_CTRL_1); | 438 | omap_writel(l, MOD_CONF_CTRL_1); |
443 | 439 | ||
444 | clk->rate = p_rate / (div + 1); | 440 | clk->rate = p_rate / (div + 1); |
445 | if (unlikely(clk->flags & RATE_PROPAGATES)) | ||
446 | propagate_rate(clk); | ||
447 | 441 | ||
448 | return 0; | 442 | return 0; |
449 | } | 443 | } |
@@ -787,7 +781,6 @@ int __init omap1_clk_init(void) | |||
787 | } | 781 | } |
788 | } | 782 | } |
789 | } | 783 | } |
790 | propagate_rate(&ck_dpll1); | ||
791 | #else | 784 | #else |
792 | /* Find the highest supported frequency and enable it */ | 785 | /* Find the highest supported frequency and enable it */ |
793 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | 786 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { |
@@ -796,9 +789,9 @@ int __init omap1_clk_init(void) | |||
796 | omap_writew(0x2290, DPLL_CTL); | 789 | omap_writew(0x2290, DPLL_CTL); |
797 | omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); | 790 | omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); |
798 | ck_dpll1.rate = 60000000; | 791 | ck_dpll1.rate = 60000000; |
799 | propagate_rate(&ck_dpll1); | ||
800 | } | 792 | } |
801 | #endif | 793 | #endif |
794 | propagate_rate(&ck_dpll1); | ||
802 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | 795 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ |
803 | propagate_rate(&ck_ref); | 796 | propagate_rate(&ck_ref); |
804 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | 797 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " |