[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach

This just leaves include/asm-arm/plat-* to deal with.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

21 files changed, 1117 insertions, 0 deletions

diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h
new file mode 100644
index 000000000000..f7e9196eb9ab
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/board.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/board.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+
+#include <asm/mach-types.h>
+
+#define board_is_a9m9750dev()   (0                      \
+                || machine_is_cc9p9360dev()             \
+                || machine_is_cc9p9750dev()             \
+                )
+
+#define board_is_a9mvali()      (0                      \
+                || machine_is_cc9p9360val()             \
+                || machine_is_cc9p9750val()             \
+                )
+
+#define board_is_jscc9p9210()   (0                      \
+                || machine_is_cc9p9210js()              \
+                )
+
+#define board_is_jscc9p9215()   (0                      \
+                || machine_is_cc9p9215js()              \
+                )
+
+#define board_is_jscc9p9360()   (0                      \
+                || machine_is_cc9p9360js()              \
+                )
+
+#define board_is_uncbas()       (0                      \
+                || machine_is_cc7ucamry()               \
+                )
+
+#endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..c9530fba00aa
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/debug-macro.S
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <mach/hardware.h>
+
+#include <mach/regs-board-a9m9750dev.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1
+                ldreq   \rx, =NS9XXX_CSxSTAT_PHYS(0)
+                ldrne   \rx, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
+                .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ns9xxx/include/mach/dma.h b/arch/arm/mach-ns9xxx/include/mach/dma.h
new file mode 100644
index 000000000000..3f50d8c9e5c7
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/dma.h
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/dma.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#endif /* ifndef __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S b/arch/arm/mach-ns9xxx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..71ca0319b547
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/entry-macro.S
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/regs-sys-common.h>
+
+                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =SYS_ISRADDR
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)]
+                cmp     \irqstat, #0
+                ldrne   \irqnr, [\base]
+                .endm
+
+                .macro  disable_fiq
+                .endm
diff --git a/arch/arm/mach-ns9xxx/include/mach/gpio.h b/arch/arm/mach-ns9xxx/include/mach/gpio.h
new file mode 100644
index 000000000000..5eb349032579
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/gpio.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/gpio.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <asm/errno.h>
+
+int gpio_request(unsigned gpio, const char *label);
+
+void gpio_free(unsigned gpio);
+
+int ns9xxx_gpio_configure(unsigned gpio, int inv, int func);
+
+int gpio_direction_input(unsigned gpio);
+
+int gpio_direction_output(unsigned gpio, int value);
+
+int gpio_get_value(unsigned gpio);
+
+void gpio_set_value(unsigned gpio, int value);
+
+/*
+ * ns9xxx can use gpio pins to trigger an irq, but it's not generic
+ * enough to be supported by the gpio_to_irq/irq_to_gpio interface
+ */
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return -EINVAL;
+}
+
+/* get the cansleep() stubs */
+#include <asm-generic/gpio.h>
+
+#endif /* ifndef __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h
new file mode 100644
index 000000000000..6dbb2030f563
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/hardware.h
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/hardware.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/memory.h>
+
+/*
+ * NetSilicon NS9xxx internal mapping:
+ *
+ * physical                <--> virtual
+ * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff
+ * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff
+ */
+#define io_p2v(x)       (0xf0000000 \
+                         + (((x) & 0xf0000000) >> 4) \
+                         + ((x) & 0x00ffffff))
+
+#define io_v2p(x)       ((((x) & 0x0f000000) << 4) \
+                         + ((x) & 0x00ffffff))
+
+#define __REGSHIFT(mask)        ((mask) & (-(mask)))
+
+#define __REGBIT(bit)           ((u32)1 << (bit))
+#define __REGBITS(hbit, lbit)   ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit))
+#define __REGVAL(mask, value)   (((value) * __REGSHIFT(mask)) & (mask))
+
+#ifndef __ASSEMBLY__
+
+#  define __REG(x)      ((void __iomem __force *)io_p2v((x)))
+#  define __REG2(x, y)  ((void __iomem __force *)(io_p2v((x)) + 4 * (y)))
+
+#  define __REGSET(var, field, value)                                   \
+        ((var) = (((var) & ~((field) & ~(value))) | (value)))
+
+#  define REGSET(var, reg, field, value)                                \
+        __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value)
+
+#  define REGSET_IDX(var, reg, field, idx, value)                       \
+        __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx)))
+
+#  define REGSETIM(var, reg, field, value)                              \
+        __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value)))
+
+#  define REGSETIM_IDX(var, reg, field, idx, value)                     \
+        __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value)))
+
+#  define __REGGET(var, field)                                          \
+        (((var) & (field)))
+
+#  define REGGET(var, reg, field)                                       \
+         __REGGET(var, reg ## _ ## field)
+
+#  define REGGET_IDX(var, reg, field, idx)                              \
+         __REGGET(var, reg ## _ ## field((idx)))
+
+#  define REGGETIM(var, reg, field)                                     \
+         __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
+
+#  define REGGETIM_IDX(var, reg, field, idx)                            \
+         __REGGET(var, reg ## _ ## field((idx))) /                      \
+         __REGSHIFT(reg ## _ ## field((idx)))
+
+#else
+
+#  define __REG(x)      io_p2v(x)
+#  define __REG2(x, y)  io_p2v((x) + 4 * (y))
+
+#endif
+
+#endif /* ifndef __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
new file mode 100644
index 000000000000..027bf649645a
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/io.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/io.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT  0xffffffff /* XXX */
+
+#define __io(a)         ((void __iomem *)(a))
+#define __mem_pci(a)    (a)
+#define __mem_isa(a)    (IO_BASE + (a))
+
+#endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/irqs.h b/arch/arm/mach-ns9xxx/include/mach/irqs.h
new file mode 100644
index 000000000000..13483949e210
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/irqs.h
@@ -0,0 +1,86 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/irqs.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+/* NetSilicon 9360 */
+#define IRQ_NS9XXX_WATCHDOG     0
+#define IRQ_NS9XXX_AHBBUSERR    1
+#define IRQ_NS9360_BBUSAGG      2
+/* irq 3 is reserved for NS9360 */
+#define IRQ_NS9XXX_ETHRX        4
+#define IRQ_NS9XXX_ETHTX        5
+#define IRQ_NS9XXX_ETHPHY       6
+#define IRQ_NS9360_LCD          7
+#define IRQ_NS9360_SERBRX       8
+#define IRQ_NS9360_SERBTX       9
+#define IRQ_NS9360_SERARX       10
+#define IRQ_NS9360_SERATX       11
+#define IRQ_NS9360_SERCRX       12
+#define IRQ_NS9360_SERCTX       13
+#define IRQ_NS9360_I2C          14
+#define IRQ_NS9360_BBUSDMA      15
+#define IRQ_NS9360_TIMER0       16
+#define IRQ_NS9360_TIMER1       17
+#define IRQ_NS9360_TIMER2       18
+#define IRQ_NS9360_TIMER3       19
+#define IRQ_NS9360_TIMER4       20
+#define IRQ_NS9360_TIMER5       21
+#define IRQ_NS9360_TIMER6       22
+#define IRQ_NS9360_TIMER7       23
+#define IRQ_NS9360_RTC          24
+#define IRQ_NS9360_USBHOST      25
+#define IRQ_NS9360_USBDEVICE    26
+#define IRQ_NS9360_IEEE1284     27
+#define IRQ_NS9XXX_EXT0         28
+#define IRQ_NS9XXX_EXT1         29
+#define IRQ_NS9XXX_EXT2         30
+#define IRQ_NS9XXX_EXT3         31
+
+#define BBUS_IRQ(irq)   (32 + irq)
+
+#define IRQ_BBUS_DMA            BBUS_IRQ(0)
+#define IRQ_BBUS_SERBRX         BBUS_IRQ(2)
+#define IRQ_BBUS_SERBTX         BBUS_IRQ(3)
+#define IRQ_BBUS_SERARX         BBUS_IRQ(4)
+#define IRQ_BBUS_SERATX         BBUS_IRQ(5)
+#define IRQ_BBUS_SERCRX         BBUS_IRQ(6)
+#define IRQ_BBUS_SERCTX         BBUS_IRQ(7)
+#define IRQ_BBUS_SERDRX         BBUS_IRQ(8)
+#define IRQ_BBUS_SERDTX         BBUS_IRQ(9)
+#define IRQ_BBUS_I2C            BBUS_IRQ(10)
+#define IRQ_BBUS_1284           BBUS_IRQ(11)
+#define IRQ_BBUS_UTIL           BBUS_IRQ(12)
+#define IRQ_BBUS_RTC            BBUS_IRQ(13)
+#define IRQ_BBUS_USBHST         BBUS_IRQ(14)
+#define IRQ_BBUS_USBDEV         BBUS_IRQ(15)
+#define IRQ_BBUS_AHBDMA1        BBUS_IRQ(24)
+#define IRQ_BBUS_AHBDMA2        BBUS_IRQ(25)
+
+/*
+ * these Interrupts are specific for the a9m9750dev board.
+ * They are generated by an FPGA that interrupts the CPU on
+ * IRQ_NS9360_EXT2
+ */
+#define FPGA_IRQ(irq)   (64 + irq)
+
+#define IRQ_FPGA_UARTA          FPGA_IRQ(0)
+#define IRQ_FPGA_UARTB          FPGA_IRQ(1)
+#define IRQ_FPGA_UARTC          FPGA_IRQ(2)
+#define IRQ_FPGA_UARTD          FPGA_IRQ(3)
+#define IRQ_FPGA_TOUCH          FPGA_IRQ(4)
+#define IRQ_FPGA_CF             FPGA_IRQ(5)
+#define IRQ_FPGA_CAN0           FPGA_IRQ(6)
+#define IRQ_FPGA_CAN1           FPGA_IRQ(7)
+
+#define NR_IRQS 72
+
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h
new file mode 100644
index 000000000000..649ee6235b94
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/memory.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/memory.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/* x in [0..3] */
+#define NS9XXX_CSxSTAT_PHYS(x)  UL(((x) + 4) << 28)
+
+#define NS9XXX_CS0STAT_LENGTH   UL(0x1000)
+#define NS9XXX_CS1STAT_LENGTH   UL(0x1000)
+#define NS9XXX_CS2STAT_LENGTH   UL(0x1000)
+#define NS9XXX_CS3STAT_LENGTH   UL(0x1000)
+
+#define PHYS_OFFSET     UL(0x00000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h
new file mode 100644
index 000000000000..f851a6b7da6c
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/module.h
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/module.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MODULE_H
+#define __ASM_ARCH_MODULE_H
+
+#include <asm/mach-types.h>
+
+#define module_is_cc7ucamry()   (0                      \
+                || machine_is_cc7ucamry()               \
+                )
+
+#define module_is_cc9c()        (0                      \
+                || machine_is_cc9c()                    \
+                )
+
+#define module_is_cc9p9210()    (0                      \
+                || machine_is_cc9p9210()                \
+                || machine_is_cc9p9210js()              \
+                )
+
+#define module_is_cc9p9215()    (0                      \
+                || machine_is_cc9p9215()                \
+                || machine_is_cc9p9215js()              \
+                )
+
+#define module_is_cc9p9360()    (0                      \
+                || machine_is_a9m9360()                 \
+                || machine_is_cc9p9360dev()             \
+                || machine_is_cc9p9360js()              \
+                || machine_is_cc9p9360val()             \
+                )
+
+#define module_is_cc9p9750()    (0                      \
+                || machine_is_a9m9750()                 \
+                || machine_is_cc9p9750dev()             \
+                || machine_is_cc9p9750js()              \
+                || machine_is_cc9p9750val()             \
+                )
+
+#define module_is_ccw9c()       (0                      \
+                || machine_is_ccw9c()                   \
+                )
+
+#define module_is_inc20otter()  (0                      \
+                || machine_is_inc20otter()              \
+                )
+
+#define module_is_otter()       (0                      \
+                || machine_is_otter()                   \
+                )
+
+#endif /* ifndef __ASM_ARCH_MODULE_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
new file mode 100644
index 000000000000..f41deda5129e
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_PROCESSORNS9360_H
+#define __ASM_ARCH_PROCESSORNS9360_H
+
+#include <linux/init.h>
+
+void ns9360_reset(char mode);
+
+unsigned long ns9360_systemclock(void) __attribute__((const));
+
+static inline unsigned long ns9360_cpuclock(void) __attribute__((const));
+static inline unsigned long ns9360_cpuclock(void)
+{
+        return ns9360_systemclock() / 2;
+}
+
+void __init ns9360_map_io(void);
+
+extern struct sys_timer ns9360_timer;
+
+int ns9360_gpio_configure(unsigned gpio, int inv, int func);
+
+#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/processor.h b/arch/arm/mach-ns9xxx/include/mach/processor.h
new file mode 100644
index 000000000000..9f77f746a386
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/processor.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/processor.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_PROCESSOR_H
+#define __ASM_ARCH_PROCESSOR_H
+
+#include <mach/module.h>
+
+#define processor_is_ns9210()   (0                      \
+                || module_is_cc7ucamry()                \
+                || module_is_cc9p9210()                 \
+                || module_is_inc20otter()               \
+                || module_is_otter()                    \
+                )
+
+#define processor_is_ns9215()   (0                      \
+                || module_is_cc9p9215()                 \
+                )
+
+#define processor_is_ns9360()   (0                      \
+                || module_is_cc9p9360()                 \
+                || module_is_cc9c()                     \
+                || module_is_ccw9c()                    \
+                )
+
+#define processor_is_ns9750()   (0                      \
+                || module_is_cc9p9750()                 \
+                )
+
+#define processor_is_ns921x()   (0                      \
+                || processor_is_ns9210()                \
+                || processor_is_ns9215()                \
+                )
+
+#endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
new file mode 100644
index 000000000000..af227c058fb9
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
@@ -0,0 +1,45 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSBBU_H
+#define __ASM_ARCH_REGSBBU_H
+
+#include <mach/hardware.h>
+
+/* BBus Utility */
+
+/* GPIO Configuration Registers block 1 */
+/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
+ * at 0 for each block.  That is, BBU_GCONFb1(0) is GPIO Configuration Register
+ * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
+#define BBU_GCONFb1(x)  __REG2(0x90600010, (x))
+#define BBU_GCONFb2(x)  __REG2(0x90600100, (x))
+
+#define BBU_GCONFx_DIR(m)       __REGBIT(3 + (((m) & 7) << 2))
+#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
+#define BBU_GCONFx_DIR_OUTPUT(m)        __REGVAL(BBU_GCONFx_DIR(m), 1)
+#define BBU_GCONFx_INV(m)       __REGBIT(2 + (((m) & 7) << 2))
+#define BBU_GCONFx_INV_NO(m)            __REGVAL(BBU_GCONFx_INV(m), 0)
+#define BBU_GCONFx_INV_YES(m)           __REGVAL(BBU_GCONFx_INV(m), 1)
+#define BBU_GCONFx_FUNC(m)      __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
+#define BBU_GCONFx_FUNC_0(m)            __REGVAL(BBU_GCONFx_FUNC(m), 0)
+#define BBU_GCONFx_FUNC_1(m)            __REGVAL(BBU_GCONFx_FUNC(m), 1)
+#define BBU_GCONFx_FUNC_2(m)            __REGVAL(BBU_GCONFx_FUNC(m), 2)
+#define BBU_GCONFx_FUNC_3(m)            __REGVAL(BBU_GCONFx_FUNC(m), 3)
+
+#define BBU_GCTRL1      __REG(0x90600030)
+#define BBU_GCTRL2      __REG(0x90600034)
+#define BBU_GCTRL3      __REG(0x90600120)
+
+#define BBU_GSTAT1      __REG(0x90600040)
+#define BBU_GSTAT2      __REG(0x90600044)
+#define BBU_GSTAT3      __REG(0x90600130)
+
+#endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h b/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
new file mode 100644
index 000000000000..cd1593693f56
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSBOARDA9M9750_H
+#define __ASM_ARCH_REGSBOARDA9M9750_H
+
+#include <mach/hardware.h>
+
+#define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0))
+#define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08)
+#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10)
+#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18)
+
+#define FPGA_IER        __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
+#define FPGA_ISR        __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
+
+#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h b/arch/arm/mach-ns9xxx/include/mach/regs-mem.h
new file mode 100644
index 000000000000..f1625bf8cdce
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-mem.h
@@ -0,0 +1,135 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-mem.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSMEM_H
+#define __ASM_ARCH_REGSMEM_H
+
+#include <mach/hardware.h>
+
+/* Memory Module */
+
+/* Control register */
+#define MEM_CTRL        __REG(0xa0700000)
+
+/* Status register */
+#define MEM_STAT        __REG(0xa0700004)
+
+/* Configuration register */
+#define MEM_CONF        __REG(0xa0700008)
+
+/* Dynamic Memory Control register */
+#define MEM_DMCTRL      __REG(0xa0700020)
+
+/* Dynamic Memory Refresh Timer */
+#define MEM_DMRT        __REG(0xa0700024)
+
+/* Dynamic Memory Read Configuration register */
+#define MEM_DMRC        __REG(0xa0700028)
+
+/* Dynamic Memory Precharge Command Period (tRP) */
+#define MEM_DMPCP       __REG(0xa0700030)
+
+/* Dynamic Memory Active to Precharge Command Period (tRAS) */
+#define MEM_DMAPCP      __REG(0xa0700034)
+
+/* Dynamic Memory Self-Refresh Exit Time (tSREX) */
+#define MEM_DMSRET      __REG(0xa0700038)
+
+/* Dynamic Memory Last Data Out to Active Time (tAPR) */
+#define MEM_DMLDOAT     __REG(0xa070003c)
+
+/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
+#define MEM_DMDIACT     __REG(0xa0700040)
+
+/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
+#define MEM_DMWRT       __REG(0xa0700044)
+
+/* Dynamic Memory Active to Active Command Period (tRC) */
+#define MEM_DMAACP      __REG(0xa0700048)
+
+/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */
+#define MEM_DMARP       __REG(0xa070004c)
+
+/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
+#define MEM_DMESRAC     __REG(0xa0700050)
+
+/* Dynamic Memory Active Bank A to Active B Time (tRRD) */
+#define MEM_DMABAABT    __REG(0xa0700054)
+
+/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
+#define MEM_DMLMACT     __REG(0xa0700058)
+
+/* Static Memory Extended Wait */
+#define MEM_SMEW        __REG(0xa0700080)
+
+/* Dynamic Memory Configuration Register x */
+#define MEM_DMCONF(x)   __REG2(0xa0700100, (x) << 3)
+
+/* Dynamic Memory RAS and CAS Delay x */
+#define MEM_DMRCD(x)    __REG2(0xa0700104, (x) << 3)
+
+/* Static Memory Configuration Register x */
+#define MEM_SMC(x)      __REG2(0xa0700200, (x) << 3)
+
+/* Static Memory Configuration Register x: Write protect */
+#define MEM_SMC_PSMC            __REGBIT(20)
+#define MEM_SMC_PSMC_OFF                __REGVAL(MEM_SMC_PSMC, 0)
+#define MEM_SMC_PSMC_ON                 __REGVAL(MEM_SMC_PSMC, 1)
+
+/* Static Memory Configuration Register x: Buffer enable */
+#define MEM_SMC_BSMC            __REGBIT(19)
+#define MEM_SMC_BSMC_OFF                __REGVAL(MEM_SMC_BSMC, 0)
+#define MEM_SMC_BSMC_ON                 __REGVAL(MEM_SMC_BSMC, 1)
+
+/* Static Memory Configuration Register x: Extended Wait */
+#define MEM_SMC_EW              __REGBIT(8)
+#define MEM_SMC_EW_OFF                  __REGVAL(MEM_SMC_EW, 0)
+#define MEM_SMC_EW_ON                   __REGVAL(MEM_SMC_EW, 1)
+
+/* Static Memory Configuration Register x: Byte lane state */
+#define MEM_SMC_PB              __REGBIT(7)
+#define MEM_SMC_PB_0                    __REGVAL(MEM_SMC_PB, 0)
+#define MEM_SMC_PB_1                    __REGVAL(MEM_SMC_PB, 1)
+
+/* Static Memory Configuration Register x: Chip select polarity */
+#define MEM_SMC_PC              __REGBIT(6)
+#define MEM_SMC_PC_AL                   __REGVAL(MEM_SMC_PC, 0)
+#define MEM_SMC_PC_AH                   __REGVAL(MEM_SMC_PC, 1)
+
+/* static memory configuration register x: page mode*/
+#define MEM_SMC_PM              __REGBIT(3)
+#define MEM_SMC_PM_DIS                  __REGVAL(MEM_SMC_PM, 0)
+#define MEM_SMC_PM_ASYNC                __REGVAL(MEM_SMC_PM, 1)
+
+/* static memory configuration register x: Memory width */
+#define MEM_SMC_MW              __REGBITS(1, 0)
+#define MEM_SMC_MW_8                    __REGVAL(MEM_SMC_MW, 0)
+#define MEM_SMC_MW_16                   __REGVAL(MEM_SMC_MW, 1)
+#define MEM_SMC_MW_32                   __REGVAL(MEM_SMC_MW, 2)
+
+/* Static Memory Write Enable Delay x */
+#define MEM_SMWED(x)    __REG2(0xa0700204, (x) << 3)
+
+/* Static Memory Output Enable Delay x */
+#define MEM_SMOED(x)    __REG2(0xa0700208, (x) << 3)
+
+/* Static Memory Read Delay x */
+#define MEM_SMRD(x)     __REG2(0xa070020c, (x) << 3)
+
+/* Static Memory Page Mode Read Delay 0 */
+#define MEM_SMPMRD(x)   __REG2(0xa0700210, (x) << 3)
+
+/* Static Memory Write Delay */
+#define MEM_SMWD(x)     __REG2(0xa0700214, (x) << 3)
+
+/* Static Memory Turn Round Delay x */
+#define MEM_SWT(x)      __REG2(0xa0700218, (x) << 3)
+
+#endif /* ifndef __ASM_ARCH_REGSMEM_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
new file mode 100644
index 000000000000..14f91dfd5736
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_REGSSYSCOMMON_H
+#define __ASM_ARCH_REGSSYSCOMMON_H
+#include <mach/hardware.h>
+
+/* Interrupt Vector Address Register Level x */
+#define SYS_IVA(x)      __REG2(0xa09000c4, (x))
+
+/* Interrupt Configuration registers */
+#define SYS_IC(x)       __REG2(0xa0900144, (x))
+
+/* ISRADDR */
+#define SYS_ISRADDR     __REG(0xa0900164)
+
+/* Interrupt Status Active */
+#define SYS_ISA         __REG(0xa0900168)
+
+/* Interrupt Status Raw */
+#define SYS_ISR         __REG(0xa090016c)
+
+#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
new file mode 100644
index 000000000000..8ff254d9901c
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
@@ -0,0 +1,148 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSSYSNS9360_H
+#define __ASM_ARCH_REGSSYSNS9360_H
+
+#include <mach/hardware.h>
+
+/* System Control Module */
+
+/* AHB Arbiter Gen Configuration */
+#define SYS_AHBAGENCONF __REG(0xa0900000)
+
+/* BRC */
+#define SYS_BRC(x)      __REG2(0xa0900004, (x))
+
+/* Timer x Reload Count register */
+#define SYS_TRC(x)      __REG2(0xa0900044, (x))
+
+/* Timer x Read register */
+#define SYS_TR(x)       __REG2(0xa0900084, (x))
+
+/* Timer Interrupt Status register */
+#define SYS_TIS         __REG(0xa0900170)
+
+/* PLL Configuration register */
+#define SYS_PLL         __REG(0xa0900188)
+
+/* PLL FS status */
+#define SYS_PLL_FS              __REGBITS(24, 23)
+
+/* PLL ND status */
+#define SYS_PLL_ND              __REGBITS(20, 16)
+
+/* PLL Configuration register: PLL SW change */
+#define SYS_PLL_SWC             __REGBIT(15)
+#define SYS_PLL_SWC_NO                  __REGVAL(SYS_PLL_SWC, 0)
+#define SYS_PLL_SWC_YES                 __REGVAL(SYS_PLL_SWC, 1)
+
+/* Timer x Control register */
+#define SYS_TC(x)       __REG2(0xa0900190, (x))
+
+/* Timer x Control register: Timer enable */
+#define SYS_TCx_TEN             __REGBIT(15)
+#define SYS_TCx_TEN_DIS                 __REGVAL(SYS_TCx_TEN, 0)
+#define SYS_TCx_TEN_EN                  __REGVAL(SYS_TCx_TEN, 1)
+
+/* Timer x Control register: CPU debug mode */
+#define SYS_TCx_TDBG            __REGBIT(10)
+#define SYS_TCx_TDBG_CONT               __REGVAL(SYS_TCx_TDBG, 0)
+#define SYS_TCx_TDBG_STOP               __REGVAL(SYS_TCx_TDBG, 1)
+
+/* Timer x Control register: Interrupt clear */
+#define SYS_TCx_INTC            __REGBIT(9)
+#define SYS_TCx_INTC_UNSET              __REGVAL(SYS_TCx_INTC, 0)
+#define SYS_TCx_INTC_SET                __REGVAL(SYS_TCx_INTC, 1)
+
+/* Timer x Control register: Timer clock select */
+#define SYS_TCx_TLCS            __REGBITS(8, 6)
+#define SYS_TCx_TLCS_CPU                __REGVAL(SYS_TCx_TLCS, 0)       /* CPU clock */
+#define SYS_TCx_TLCS_DIV2               __REGVAL(SYS_TCx_TLCS, 1)       /* CPU clock / 2 */
+#define SYS_TCx_TLCS_DIV4               __REGVAL(SYS_TCx_TLCS, 2)       /* CPU clock / 4 */
+#define SYS_TCx_TLCS_DIV8               __REGVAL(SYS_TCx_TLCS, 3)       /* CPU clock / 8 */
+#define SYS_TCx_TLCS_DIV16              __REGVAL(SYS_TCx_TLCS, 4)       /* CPU clock / 16 */
+#define SYS_TCx_TLCS_DIV32              __REGVAL(SYS_TCx_TLCS, 5)       /* CPU clock / 32 */
+#define SYS_TCx_TLCS_DIV64              __REGVAL(SYS_TCx_TLCS, 6)       /* CPU clock / 64 */
+#define SYS_TCx_TLCS_EXT                __REGVAL(SYS_TCx_TLCS, 7)
+
+/* Timer x Control register: Timer mode */
+#define SYS_TCx_TM              __REGBITS(5, 4)
+#define SYS_TCx_TM_IEE                  __REGVAL(SYS_TCx_TM, 0)         /* Internal timer or external event */
+#define SYS_TCx_TM_ELL                  __REGVAL(SYS_TCx_TM, 1)         /* External low-level, gated timer */
+#define SYS_TCx_TM_EHL                  __REGVAL(SYS_TCx_TM, 2)         /* External high-level, gated timer */
+#define SYS_TCx_TM_CONCAT               __REGVAL(SYS_TCx_TM, 3)         /* Concatenate the lower timer. */
+
+/* Timer x Control register: Interrupt select */
+#define SYS_TCx_INTS            __REGBIT(3)
+#define SYS_TCx_INTS_DIS                __REGVAL(SYS_TCx_INTS, 0)
+#define SYS_TCx_INTS_EN                 __REGVAL(SYS_TCx_INTS, 1)
+
+/* Timer x Control register: Up/down select */
+#define SYS_TCx_UDS             __REGBIT(2)
+#define SYS_TCx_UDS_UP                  __REGVAL(SYS_TCx_UDS, 0)
+#define SYS_TCx_UDS_DOWN                __REGVAL(SYS_TCx_UDS, 1)
+
+/* Timer x Control register: 32- or 16-bit timer */
+#define SYS_TCx_TSZ             __REGBIT(1)
+#define SYS_TCx_TSZ_16                  __REGVAL(SYS_TCx_TSZ, 0)
+#define SYS_TCx_TSZ_32                  __REGVAL(SYS_TCx_TSZ, 1)
+
+/* Timer x Control register: Reload enable */
+#define SYS_TCx_REN             __REGBIT(0)
+#define SYS_TCx_REN_DIS                 __REGVAL(SYS_TCx_REN, 0)
+#define SYS_TCx_REN_EN                  __REGVAL(SYS_TCx_REN, 1)
+
+/* System Memory Chip Select x Dynamic Memory Base */
+#define SYS_SMCSDMB(x)  __REG2(0xa09001d0, (x) << 1)
+
+/* System Memory Chip Select x Dynamic Memory Mask */
+#define SYS_SMCSDMM(x)  __REG2(0xa09001d4, (x) << 1)
+
+/* System Memory Chip Select x Static Memory Base */
+#define SYS_SMCSSMB(x)  __REG2(0xa09001f0, (x) << 1)
+
+/* System Memory Chip Select x Static Memory Base: Chip select x base */
+#define SYS_SMCSSMB_CSxB        __REGBITS(31, 12)
+
+/* System Memory Chip Select x Static Memory Mask */
+#define SYS_SMCSSMM(x)  __REG2(0xa09001f4, (x) << 1)
+
+/* System Memory Chip Select x Static Memory Mask: Chip select x mask */
+#define SYS_SMCSSMM_CSxM        __REGBITS(31, 12)
+
+/* System Memory Chip Select x Static Memory Mask: Chip select x enable */
+#define SYS_SMCSSMM_CSEx        __REGBIT(0)
+#define SYS_SMCSSMM_CSEx_DIS            __REGVAL(SYS_SMCSSMM_CSEx, 0)
+#define SYS_SMCSSMM_CSEx_EN             __REGVAL(SYS_SMCSSMM_CSEx, 1)
+
+/* General purpose, user-defined ID register */
+#define SYS_GENID       __REG(0xa0900210)
+
+/* External Interrupt x Control register */
+#define SYS_EIC(x)      __REG2(0xa0900214, (x))
+
+/* External Interrupt x Control register: Status */
+#define SYS_EIC_STS             __REGBIT(3)
+
+/* External Interrupt x Control register: Clear */
+#define SYS_EIC_CLR             __REGBIT(2)
+
+/* External Interrupt x Control register: Polarity */
+#define SYS_EIC_PLTY            __REGBIT(1)
+#define SYS_EIC_PLTY_AH                 __REGVAL(SYS_EIC_PLTY, 0)
+#define SYS_EIC_PLTY_AL                 __REGVAL(SYS_EIC_PLTY, 1)
+
+/* External Interrupt x Control register: Level edge */
+#define SYS_EIC_LVEDG           __REGBIT(0)
+#define SYS_EIC_LVEDG_LEVEL             __REGVAL(SYS_EIC_LVEDG, 0)
+#define SYS_EIC_LVEDG_EDGE              __REGVAL(SYS_EIC_LVEDG, 1)
+
+#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h
new file mode 100644
index 000000000000..e2068c57415f
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/system.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/system.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/proc-fns.h>
+#include <mach/processor.h>
+#include <mach/processor-ns9360.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+#ifdef CONFIG_PROCESSOR_NS9360
+        if (processor_is_ns9360())
+                ns9360_reset(mode);
+        else
+#endif
+                BUG();
+
+        BUG();
+}
+
+#endif /* ifndef __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/timex.h b/arch/arm/mach-ns9xxx/include/mach/timex.h
new file mode 100644
index 000000000000..734a8d8bd578
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/timex.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/timex.h
+ *
+ * Copyright (C) 2005-2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/*
+ * value for CLOCK_TICK_RATE stolen from arch/arm/mach-s3c2410/include/mach/timex.h.
+ * See there for an explanation.
+ */
+#define CLOCK_TICK_RATE         12000000
+
+#endif /* ifndef __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
new file mode 100644
index 000000000000..5dbc3c5167c8
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
@@ -0,0 +1,164 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/uncompress.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/io.h>
+
+#define __REG(x)        ((void __iomem __force *)(x))
+
+static void putc_dummy(char c, void __iomem *base)
+{
+        /* nothing */
+}
+
+static void putc_ns9360(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+
+                if (__raw_readl(base + 8) & (1 << 3)) {
+                        __raw_writeb(c, base + 16);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+}
+
+static void putc_a9m9750dev(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+
+                if (__raw_readb(base + 5) & (1 << 5)) {
+                        __raw_writeb(c, base);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+
+}
+
+static void putc_ns921x(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+
+                if (!(__raw_readl(base) & (1 << 11))) {
+                        __raw_writeb(c, base + 0x0028);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+}
+
+#define MSCS __REG(0xA0900184)
+
+#define NS9360_UARTA    __REG(0x90200040)
+#define NS9360_UARTB    __REG(0x90200000)
+#define NS9360_UARTC    __REG(0x90300000)
+#define NS9360_UARTD    __REG(0x90300040)
+
+#define NS9360_UART_ENABLED(base)                                       \
+                (__raw_readl(NS9360_UARTA) & (1 << 31))
+
+#define A9M9750DEV_UARTA        __REG(0x40000000)
+
+#define NS921XSYS_CLOCK __REG(0xa090017c)
+#define NS921X_UARTA    __REG(0x90010000)
+#define NS921X_UARTB    __REG(0x90018000)
+#define NS921X_UARTC    __REG(0x90020000)
+#define NS921X_UARTD    __REG(0x90028000)
+
+#define NS921X_UART_ENABLED(base)                                       \
+                (__raw_readl((base) + 0x1000) & (1 << 29))
+
+static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
+{
+        if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
+                /* ns9360 or ns9750 */
+                if (NS9360_UART_ENABLED(NS9360_UARTA)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTA;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTB)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTB;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTC)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTC;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTD)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTD;
+                        return;
+                } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) {
+                        *putc = putc_a9m9750dev;
+                        *base = A9M9750DEV_UARTA;
+                        return;
+                }
+        } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) {
+                /* ns921x */
+                u32 clock = __raw_readl(NS921XSYS_CLOCK);
+
+                if ((clock & (1 << 1)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTA)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTA;
+                        return;
+                } else if ((clock & (1 << 2)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTB)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTB;
+                        return;
+                } else if ((clock & (1 << 3)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTC)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTC;
+                        return;
+                } else if ((clock & (1 << 4)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTD)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTD;
+                        return;
+                }
+        }
+
+        *putc = putc_dummy;
+}
+
+void (*myputc)(char, void __iomem *);
+void __iomem *base;
+
+static void putc(char c)
+{
+        myputc(c, base);
+}
+
+static void arch_decomp_setup(void)
+{
+        autodetect(&myputc, &base);
+}
+#define arch_decomp_wdog()
+
+static void flush(void)
+{
+        /* nothing */
+}
+
+#endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..fe964d3bcc47
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ * arch/arm/mach-ns9xxx/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2006 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END     (0xf0000000)
+
+#endif /* ifndef __ASM_ARCH_VMALLOC_H */