diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2013-01-02 16:30:56 -0500 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2013-01-03 17:42:07 -0500 |
commit | d9621176872319a568d9892701410bcbfbd5b35c (patch) | |
tree | b5f2d4303a746f634e9700e3d62c8291bd4320f0 /arch/arm/mach-nomadik | |
parent | 7f252b162841d42d0a629d37450522ae75c46890 (diff) |
ARM: nomadik: bump the IRQ numbers again
Bump the IRQ numbers from offset at 1 (right above NO_IRQ)
to 32. This is the painful way to learn that if you're using
SPARSE_IRQ and avoid to define .nr_irqs in your machine,
the first 16 IRQs will be pre-allocated, and the IRQdomain
code (as the VIC core code before it) will then assume
that all IRQ descriptors are pre-allocated, and 16 of them
are - by somebody else. So mapping the IRQs will fail in
irq_create_mapping(). Moving the offset upward rids us of
this problem.
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-nomadik')
-rw-r--r-- | arch/arm/mach-nomadik/include/mach/irqs.h | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h index b549d0571548..215f8cdb4004 100644 --- a/arch/arm/mach-nomadik/include/mach/irqs.h +++ b/arch/arm/mach-nomadik/include/mach/irqs.h | |||
@@ -22,49 +22,49 @@ | |||
22 | 22 | ||
23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
24 | 24 | ||
25 | #define IRQ_VIC_START 1 /* first VIC interrupt is 1 */ | 25 | #define IRQ_VIC_START 32 /* first VIC interrupt is 1 */ |
26 | 26 | ||
27 | /* | 27 | /* |
28 | * Interrupt numbers generic for all Nomadik Chip cuts | 28 | * Interrupt numbers generic for all Nomadik Chip cuts |
29 | */ | 29 | */ |
30 | #define IRQ_WATCHDOG 1 | 30 | #define IRQ_WATCHDOG (IRQ_VIC_START+0) |
31 | #define IRQ_SOFTINT 2 | 31 | #define IRQ_SOFTINT (IRQ_VIC_START+1) |
32 | #define IRQ_CRYPTO 3 | 32 | #define IRQ_CRYPTO (IRQ_VIC_START+2) |
33 | #define IRQ_OWM 4 | 33 | #define IRQ_OWM (IRQ_VIC_START+3) |
34 | #define IRQ_MTU0 5 | 34 | #define IRQ_MTU0 (IRQ_VIC_START+4) |
35 | #define IRQ_MTU1 6 | 35 | #define IRQ_MTU1 (IRQ_VIC_START+5) |
36 | #define IRQ_GPIO0 7 | 36 | #define IRQ_GPIO0 (IRQ_VIC_START+6) |
37 | #define IRQ_GPIO1 8 | 37 | #define IRQ_GPIO1 (IRQ_VIC_START+7) |
38 | #define IRQ_GPIO2 9 | 38 | #define IRQ_GPIO2 (IRQ_VIC_START+8) |
39 | #define IRQ_GPIO3 10 | 39 | #define IRQ_GPIO3 (IRQ_VIC_START+9) |
40 | #define IRQ_RTC_RTT 11 | 40 | #define IRQ_RTC_RTT (IRQ_VIC_START+10) |
41 | #define IRQ_SSP 12 | 41 | #define IRQ_SSP (IRQ_VIC_START+11) |
42 | #define IRQ_UART0 13 | 42 | #define IRQ_UART0 (IRQ_VIC_START+12) |
43 | #define IRQ_DMA1 14 | 43 | #define IRQ_DMA1 (IRQ_VIC_START+13) |
44 | #define IRQ_CLCD_MDIF 15 | 44 | #define IRQ_CLCD_MDIF (IRQ_VIC_START+14) |
45 | #define IRQ_DMA0 16 | 45 | #define IRQ_DMA0 (IRQ_VIC_START+15) |
46 | #define IRQ_PWRFAIL 17 | 46 | #define IRQ_PWRFAIL (IRQ_VIC_START+16) |
47 | #define IRQ_UART1 18 | 47 | #define IRQ_UART1 (IRQ_VIC_START+17) |
48 | #define IRQ_FIRDA 19 | 48 | #define IRQ_FIRDA (IRQ_VIC_START+18) |
49 | #define IRQ_MSP0 20 | 49 | #define IRQ_MSP0 (IRQ_VIC_START+19) |
50 | #define IRQ_I2C0 21 | 50 | #define IRQ_I2C0 (IRQ_VIC_START+20) |
51 | #define IRQ_I2C1 22 | 51 | #define IRQ_I2C1 (IRQ_VIC_START+21) |
52 | #define IRQ_SDMMC 23 | 52 | #define IRQ_SDMMC (IRQ_VIC_START+22) |
53 | #define IRQ_USBOTG 24 | 53 | #define IRQ_USBOTG (IRQ_VIC_START+23) |
54 | #define IRQ_SVA_IT0 25 | 54 | #define IRQ_SVA_IT0 (IRQ_VIC_START+24) |
55 | #define IRQ_SVA_IT1 26 | 55 | #define IRQ_SVA_IT1 (IRQ_VIC_START+25) |
56 | #define IRQ_SAA_IT0 27 | 56 | #define IRQ_SAA_IT0 (IRQ_VIC_START+26) |
57 | #define IRQ_SAA_IT1 28 | 57 | #define IRQ_SAA_IT1 (IRQ_VIC_START+27) |
58 | #define IRQ_UART2 29 | 58 | #define IRQ_UART2 (IRQ_VIC_START+28) |
59 | #define IRQ_MSP2 30 | 59 | #define IRQ_MSP2 (IRQ_VIC_START+29) |
60 | #define IRQ_L2CC 49 | 60 | #define IRQ_L2CC (IRQ_VIC_START+30) |
61 | #define IRQ_HPI 50 | 61 | #define IRQ_HPI (IRQ_VIC_START+31) |
62 | #define IRQ_SKE 51 | 62 | #define IRQ_SKE (IRQ_VIC_START+32) |
63 | #define IRQ_KP 52 | 63 | #define IRQ_KP (IRQ_VIC_START+33) |
64 | #define IRQ_MEMST 55 | 64 | #define IRQ_MEMST (IRQ_VIC_START+34) |
65 | #define IRQ_SGA_IT 59 | 65 | #define IRQ_SGA_IT (IRQ_VIC_START+35) |
66 | #define IRQ_USBM 61 | 66 | #define IRQ_USBM (IRQ_VIC_START+36) |
67 | #define IRQ_MSP1 63 | 67 | #define IRQ_MSP1 (IRQ_VIC_START+37) |
68 | 68 | ||
69 | #define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64) | 69 | #define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64) |
70 | 70 | ||