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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-17 22:08:06 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-17 22:08:06 -0400
commit411f5c7a502769ccc0377c5ba36cb0b283847ba8 (patch)
tree2c3a29671e3f923de48c55f94194849264a7bf53 /arch/arm/mach-mxs
parent6d7ed21d17e640b120b902a314143e5ef4917a70 (diff)
parent9ced9f03d12d7539e86b0bff5bc750153c976c34 (diff)
Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (289 commits) davinci: DM644x EVM: register MUSB device earlier davinci: add spi devices on tnetv107x evm davinci: add ssp config for tnetv107x evm board davinci: add tnetv107x ssp platform device spi: add ti-ssp spi master driver mfd: add driver for sequencer serial port ARM: EXYNOS4: Implement Clock gating for System MMU ARM: EXYNOS4: Enhancement of System MMU driver ARM: EXYNOS4: Add support for gpio interrupts ARM: S5P: Add function to register gpio interrupt bank data ARM: S5P: Cleanup S5P gpio interrupt code ARM: EXYNOS4: Add missing GPYx banks ARM: S3C64XX: Fix section mismatch from cpufreq init ARM: EXYNOS4: Add keypad device to the SMDKV310 ARM: EXYNOS4: Update clocks for keypad ARM: EXYNOS4: Update keypad base address ARM: EXYNOS4: Add keypad device helpers ARM: EXYNOS4: Add support for SATA on ARMLEX4210 plat-nomadik: make GPIO interrupts work with cpuidle ApSleep mach-u300: define a dummy filter function for coh901318 ... Fix up various conflicts in - arch/arm/mach-exynos4/cpufreq.c - arch/arm/mach-mxs/gpio.c - drivers/net/Kconfig - drivers/tty/serial/Kconfig - drivers/tty/serial/Makefile - drivers/usb/gadget/fsl_mxc_udc.c - drivers/video/Kconfig
Diffstat (limited to 'arch/arm/mach-mxs')
-rw-r--r--arch/arm/mach-mxs/Kconfig24
-rw-r--r--arch/arm/mach-mxs/Makefile5
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c11
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c25
-rw-r--r--arch/arm/mach-mxs/devices-mx23.h11
-rw-r--r--arch/arm/mach-mxs/devices-mx28.h23
-rw-r--r--arch/arm/mach-mxs/devices.c2
-rw-r--r--arch/arm/mach-mxs/devices/Kconfig16
-rw-r--r--arch/arm/mach-mxs/devices/Makefile6
-rw-r--r--arch/arm/mach-mxs/devices/platform-auart.c64
-rw-r--r--arch/arm/mach-mxs/devices/platform-dma.c49
-rw-r--r--arch/arm/mach-mxs/devices/platform-fec.c5
-rw-r--r--arch/arm/mach-mxs/devices/platform-flexcan.c51
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxs-i2c.c51
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxs-pwm.c22
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxsfb.c46
-rw-r--r--arch/arm/mach-mxs/gpio.c46
-rw-r--r--arch/arm/mach-mxs/include/mach/common.h1
-rw-r--r--arch/arm/mach-mxs/include/mach/devices-common.h35
-rw-r--r--arch/arm/mach-mxs/include/mach/iomux-mx23.h190
-rw-r--r--arch/arm/mach-mxs/include/mach/iomux.h3
-rw-r--r--arch/arm/mach-mxs/include/mach/mx23.h38
-rw-r--r--arch/arm/mach-mxs/include/mach/mx28.h45
-rw-r--r--arch/arm/mach-mxs/include/mach/mxs.h9
-rw-r--r--arch/arm/mach-mxs/include/mach/mxsfb.h49
-rw-r--r--arch/arm/mach-mxs/include/mach/uncompress.h1
-rw-r--r--arch/arm/mach-mxs/mach-mx23evk.c90
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c237
-rw-r--r--arch/arm/mach-mxs/mach-tx28.c183
-rw-r--r--arch/arm/mach-mxs/module-tx28.c131
-rw-r--r--arch/arm/mach-mxs/module-tx28.h9
-rw-r--r--arch/arm/mach-mxs/ocotp.c90
-rw-r--r--arch/arm/mach-mxs/pm.c43
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx23.h124
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx28.h177
-rw-r--r--arch/arm/mach-mxs/system.c2
36 files changed, 1434 insertions, 480 deletions
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 8bfc8df54617..4f6f174af6c8 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -2,13 +2,18 @@ if ARCH_MXS
2 2
3source "arch/arm/mach-mxs/devices/Kconfig" 3source "arch/arm/mach-mxs/devices/Kconfig"
4 4
5config MXS_OCOTP
6 bool
7
5config SOC_IMX23 8config SOC_IMX23
6 bool 9 bool
7 select CPU_ARM926T 10 select CPU_ARM926T
11 select HAVE_PWM
8 12
9config SOC_IMX28 13config SOC_IMX28
10 bool 14 bool
11 select CPU_ARM926T 15 select CPU_ARM926T
16 select HAVE_PWM
12 17
13comment "MXS platforms:" 18comment "MXS platforms:"
14 19
@@ -16,6 +21,8 @@ config MACH_MX23EVK
16 bool "Support MX23EVK Platform" 21 bool "Support MX23EVK Platform"
17 select SOC_IMX23 22 select SOC_IMX23
18 select MXS_HAVE_AMBA_DUART 23 select MXS_HAVE_AMBA_DUART
24 select MXS_HAVE_PLATFORM_AUART
25 select MXS_HAVE_PLATFORM_MXSFB
19 default y 26 default y
20 help 27 help
21 Include support for MX23EVK platform. This includes specific 28 Include support for MX23EVK platform. This includes specific
@@ -25,10 +32,27 @@ config MACH_MX28EVK
25 bool "Support MX28EVK Platform" 32 bool "Support MX28EVK Platform"
26 select SOC_IMX28 33 select SOC_IMX28
27 select MXS_HAVE_AMBA_DUART 34 select MXS_HAVE_AMBA_DUART
35 select MXS_HAVE_PLATFORM_AUART
28 select MXS_HAVE_PLATFORM_FEC 36 select MXS_HAVE_PLATFORM_FEC
37 select MXS_HAVE_PLATFORM_FLEXCAN
38 select MXS_HAVE_PLATFORM_MXSFB
39 select MXS_OCOTP
29 default y 40 default y
30 help 41 help
31 Include support for MX28EVK platform. This includes specific 42 Include support for MX28EVK platform. This includes specific
32 configurations for the board and its peripherals. 43 configurations for the board and its peripherals.
33 44
45config MODULE_TX28
46 bool
47 select SOC_IMX28
48 select MXS_HAVE_AMBA_DUART
49 select MXS_HAVE_PLATFORM_AUART
50 select MXS_HAVE_PLATFORM_FEC
51 select MXS_HAVE_PLATFORM_MXS_I2C
52 select MXS_HAVE_PLATFORM_MXS_PWM
53
54config MACH_TX28
55 bool "Ka-Ro TX28 module"
56 select MODULE_TX28
57
34endif 58endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 39d3f9c2a841..2f1f6141ca71 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,10 +1,15 @@
1# Common support 1# Common support
2obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o 2obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
3 3
4obj-$(CONFIG_MXS_OCOTP) += ocotp.o
5obj-$(CONFIG_PM) += pm.o
6
4obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o 7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
5obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o 8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
6 9
7obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 10obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
8obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o 11obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
12obj-$(CONFIG_MODULE_TX28) += module-tx28.o
13obj-$(CONFIG_MACH_TX28) += mach-tx28.o
9 14
10obj-y += devices/ 15obj-y += devices/
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index ca72a05ed9c1..d133c7f30940 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -442,11 +442,18 @@ static struct clk_lookup lookups[] = {
442 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk) 442 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
443 /* for amba-pl011 driver */ 443 /* for amba-pl011 driver */
444 _REGISTER_CLOCK("duart", NULL, uart_clk) 444 _REGISTER_CLOCK("duart", NULL, uart_clk)
445 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
445 _REGISTER_CLOCK("rtc", NULL, rtc_clk) 446 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
446 _REGISTER_CLOCK(NULL, "hclk", hbus_clk) 447 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
448 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
447 _REGISTER_CLOCK(NULL, "usb", usb_clk) 449 _REGISTER_CLOCK(NULL, "usb", usb_clk)
448 _REGISTER_CLOCK(NULL, "audio", audio_clk) 450 _REGISTER_CLOCK(NULL, "audio", audio_clk)
449 _REGISTER_CLOCK(NULL, "pwm", pwm_clk) 451 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
452 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
453 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
454 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
455 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
456 _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
450}; 457};
451 458
452static int clk_misc_init(void) 459static int clk_misc_init(void)
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index fd1c4c54b8e5..5e489a2b2023 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -609,17 +609,30 @@ static struct clk_lookup lookups[] = {
609 _REGISTER_CLOCK("duart", NULL, uart_clk) 609 _REGISTER_CLOCK("duart", NULL, uart_clk)
610 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk) 610 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
611 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk) 611 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
612 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
613 _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
614 _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
615 _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
616 _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
612 _REGISTER_CLOCK("rtc", NULL, rtc_clk) 617 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
613 _REGISTER_CLOCK("pll2", NULL, pll2_clk) 618 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
614 _REGISTER_CLOCK(NULL, "hclk", hbus_clk) 619 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
615 _REGISTER_CLOCK(NULL, "xclk", xbus_clk) 620 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
616 _REGISTER_CLOCK(NULL, "can0", can0_clk) 621 _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
617 _REGISTER_CLOCK(NULL, "can1", can1_clk) 622 _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
618 _REGISTER_CLOCK(NULL, "usb0", usb0_clk) 623 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
619 _REGISTER_CLOCK(NULL, "usb1", usb1_clk) 624 _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
620 _REGISTER_CLOCK(NULL, "pwm", pwm_clk) 625 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
626 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
627 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
628 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
629 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
630 _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
631 _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
632 _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
621 _REGISTER_CLOCK(NULL, "lradc", lradc_clk) 633 _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
622 _REGISTER_CLOCK(NULL, "spdif", spdif_clk) 634 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
635 _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
623}; 636};
624 637
625static int clk_misc_init(void) 638static int clk_misc_init(void)
@@ -737,6 +750,8 @@ int __init mx28_clocks_init(void)
737 clk_enable(&emi_clk); 750 clk_enable(&emi_clk);
738 clk_enable(&uart_clk); 751 clk_enable(&uart_clk);
739 752
753 clk_set_parent(&lcdif_clk, &ref_pix_clk);
754
740 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 755 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
741 756
742 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0); 757 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 1256788561d0..c7e14f4e3669 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -10,7 +10,18 @@
10 */ 10 */
11#include <mach/mx23.h> 11#include <mach/mx23.h>
12#include <mach/devices-common.h> 12#include <mach/devices-common.h>
13#include <mach/mxsfb.h>
13 14
14extern const struct amba_device mx23_duart_device __initconst; 15extern const struct amba_device mx23_duart_device __initconst;
15#define mx23_add_duart() \ 16#define mx23_add_duart() \
16 mxs_add_duart(&mx23_duart_device) 17 mxs_add_duart(&mx23_duart_device)
18
19extern const struct mxs_auart_data mx23_auart_data[] __initconst;
20#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id])
21#define mx23_add_auart0() mx23_add_auart(0)
22#define mx23_add_auart1() mx23_add_auart(1)
23
24#define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
25
26struct platform_device *__init mx23_add_mxsfb(
27 const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 33773a6333a2..9d08555c4cf0 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -10,11 +10,34 @@
10 */ 10 */
11#include <mach/mx28.h> 11#include <mach/mx28.h>
12#include <mach/devices-common.h> 12#include <mach/devices-common.h>
13#include <mach/mxsfb.h>
13 14
14extern const struct amba_device mx28_duart_device __initconst; 15extern const struct amba_device mx28_duart_device __initconst;
15#define mx28_add_duart() \ 16#define mx28_add_duart() \
16 mxs_add_duart(&mx28_duart_device) 17 mxs_add_duart(&mx28_duart_device)
17 18
19extern const struct mxs_auart_data mx28_auart_data[] __initconst;
20#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id])
21#define mx28_add_auart0() mx28_add_auart(0)
22#define mx28_add_auart1() mx28_add_auart(1)
23#define mx28_add_auart2() mx28_add_auart(2)
24#define mx28_add_auart3() mx28_add_auart(3)
25#define mx28_add_auart4() mx28_add_auart(4)
26
18extern const struct mxs_fec_data mx28_fec_data[] __initconst; 27extern const struct mxs_fec_data mx28_fec_data[] __initconst;
19#define mx28_add_fec(id, pdata) \ 28#define mx28_add_fec(id, pdata) \
20 mxs_add_fec(&mx28_fec_data[id], pdata) 29 mxs_add_fec(&mx28_fec_data[id], pdata)
30
31extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
32#define mx28_add_flexcan(id, pdata) \
33 mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
34#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata)
35#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata)
36
37extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
38#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
39
40#define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
41
42struct platform_device *__init mx28_add_mxsfb(
43 const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index c20d54740b0b..cfdb6b284702 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -66,6 +66,8 @@ struct platform_device *__init mxs_add_platform_device_dmamask(
66 ret = platform_device_add(pdev); 66 ret = platform_device_add(pdev);
67 if (ret) { 67 if (ret) {
68err: 68err:
69 if (dmamask)
70 kfree(pdev->dev.dma_mask);
69 platform_device_put(pdev); 71 platform_device_put(pdev);
70 return ERR_PTR(ret); 72 return ERR_PTR(ret);
71 } 73 }
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index cf7dc1ae575b..1451ad060d82 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -2,5 +2,21 @@ config MXS_HAVE_AMBA_DUART
2 bool 2 bool
3 select ARM_AMBA 3 select ARM_AMBA
4 4
5config MXS_HAVE_PLATFORM_AUART
6 bool
7
5config MXS_HAVE_PLATFORM_FEC 8config MXS_HAVE_PLATFORM_FEC
6 bool 9 bool
10
11config MXS_HAVE_PLATFORM_FLEXCAN
12 select HAVE_CAN_FLEXCAN if CAN
13 bool
14
15config MXS_HAVE_PLATFORM_MXS_I2C
16 bool
17
18config MXS_HAVE_PLATFORM_MXS_PWM
19 bool
20
21config MXS_HAVE_PLATFORM_MXSFB
22 bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index d0a09f6934b8..0d9bea30b0a2 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -1,2 +1,8 @@
1obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o 1obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
2obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
3obj-y += platform-dma.o
2obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o 4obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
5obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
6obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
7obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
8obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
new file mode 100644
index 000000000000..796606cce0ce
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-auart.c
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx23.h>
11#include <mach/mx28.h>
12#include <mach/devices-common.h>
13
14#define mxs_auart_data_entry_single(soc, _id, hwid) \
15 { \
16 .id = _id, \
17 .iobase = soc ## _AUART ## hwid ## _BASE_ADDR, \
18 .irq = soc ## _INT_AUART ## hwid, \
19 }
20
21#define mxs_auart_data_entry(soc, _id, hwid) \
22 [_id] = mxs_auart_data_entry_single(soc, _id, hwid)
23
24#ifdef CONFIG_SOC_IMX23
25const struct mxs_auart_data mx23_auart_data[] __initconst = {
26#define mx23_auart_data_entry(_id, hwid) \
27 mxs_auart_data_entry(MX23, _id, hwid)
28 mx23_auart_data_entry(0, 1),
29 mx23_auart_data_entry(1, 2),
30};
31#endif
32
33#ifdef CONFIG_SOC_IMX28
34const struct mxs_auart_data mx28_auart_data[] __initconst = {
35#define mx28_auart_data_entry(_id) \
36 mxs_auart_data_entry(MX28, _id, _id)
37 mx28_auart_data_entry(0),
38 mx28_auart_data_entry(1),
39 mx28_auart_data_entry(2),
40 mx28_auart_data_entry(3),
41 mx28_auart_data_entry(4),
42};
43#endif
44
45struct platform_device *__init mxs_add_auart(
46 const struct mxs_auart_data *data)
47{
48 struct resource res[] = {
49 {
50 .start = data->iobase,
51 .end = data->iobase + SZ_8K - 1,
52 .flags = IORESOURCE_MEM,
53 }, {
54 .start = data->irq,
55 .end = data->irq,
56 .flags = IORESOURCE_IRQ,
57 },
58 };
59
60 return mxs_add_platform_device_dmamask("mxs-auart", data->id,
61 res, ARRAY_SIZE(res), NULL, 0,
62 DMA_BIT_MASK(32));
63}
64
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
new file mode 100644
index 000000000000..295c4424d5d9
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-dma.c
@@ -0,0 +1,49 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <linux/compiler.h>
9#include <linux/err.h>
10#include <linux/init.h>
11
12#include <mach/mx23.h>
13#include <mach/mx28.h>
14#include <mach/devices-common.h>
15
16static struct platform_device *__init mxs_add_dma(const char *devid,
17 resource_size_t base)
18{
19 struct resource res[] = {
20 {
21 .start = base,
22 .end = base + SZ_8K - 1,
23 .flags = IORESOURCE_MEM,
24 }
25 };
26
27 return mxs_add_platform_device_dmamask(devid, -1,
28 res, ARRAY_SIZE(res), NULL, 0,
29 DMA_BIT_MASK(32));
30}
31
32static int __init mxs_add_mxs_dma(void)
33{
34 char *apbh = "mxs-dma-apbh";
35 char *apbx = "mxs-dma-apbx";
36
37 if (cpu_is_mx23()) {
38 mxs_add_dma(apbh, MX23_APBH_DMA_BASE_ADDR);
39 mxs_add_dma(apbx, MX23_APBX_DMA_BASE_ADDR);
40 }
41
42 if (cpu_is_mx28()) {
43 mxs_add_dma(apbh, MX28_APBH_DMA_BASE_ADDR);
44 mxs_add_dma(apbx, MX28_APBX_DMA_BASE_ADDR);
45 }
46
47 return 0;
48}
49arch_initcall(mxs_add_mxs_dma);
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
index c42dff72b46c..9859cf283335 100644
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -45,6 +45,7 @@ struct platform_device *__init mxs_add_fec(
45 }, 45 },
46 }; 46 };
47 47
48 return mxs_add_platform_device("imx28-fec", data->id, 48 return mxs_add_platform_device_dmamask("imx28-fec", data->id,
49 res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); 49 res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
50 DMA_BIT_MASK(32));
50} 51}
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c
new file mode 100644
index 000000000000..43a6b4bae6fe
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-flexcan.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2010, 2011 Pengutronix,
3 * Marc Kleine-Budde <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12
13#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \
17 .iosize = _size, \
18 .irq = soc ## _INT_CAN ## _hwid, \
19 }
20
21#define mxs_flexcan_data_entry(soc, _id, _hwid, _size) \
22 [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)
23
24#ifdef CONFIG_SOC_IMX28
25const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = {
26#define mx28_flexcan_data_entry(_id, _hwid) \
27 mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K)
28 mx28_flexcan_data_entry(0, 0),
29 mx28_flexcan_data_entry(1, 1),
30};
31#endif /* ifdef CONFIG_SOC_IMX28 */
32
33struct platform_device *__init mxs_add_flexcan(
34 const struct mxs_flexcan_data *data,
35 const struct flexcan_platform_data *pdata)
36{
37 struct resource res[] = {
38 {
39 .start = data->iobase,
40 .end = data->iobase + data->iosize - 1,
41 .flags = IORESOURCE_MEM,
42 }, {
43 .start = data->irq,
44 .end = data->irq,
45 .flags = IORESOURCE_IRQ,
46 },
47 };
48
49 return mxs_add_platform_device("flexcan", data->id,
50 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
51}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
new file mode 100644
index 000000000000..eab3a06836d6
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2011 Pengutronix
3 * Wolfram Sang <w.sang@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12
13#define mxs_i2c_data_entry_single(soc, _id) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _I2C ## _id ## _BASE_ADDR, \
17 .errirq = soc ## _INT_I2C ## _id ## _ERROR, \
18 .dmairq = soc ## _INT_I2C ## _id ## _DMA, \
19 }
20
21#define mxs_i2c_data_entry(soc, _id) \
22 [_id] = mxs_i2c_data_entry_single(soc, _id)
23
24#ifdef CONFIG_SOC_IMX28
25const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
26 mxs_i2c_data_entry(MX28, 0),
27 mxs_i2c_data_entry(MX28, 1),
28};
29#endif
30
31struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data)
32{
33 struct resource res[] = {
34 {
35 .start = data->iobase,
36 .end = data->iobase + SZ_8K - 1,
37 .flags = IORESOURCE_MEM,
38 }, {
39 .start = data->errirq,
40 .end = data->errirq,
41 .flags = IORESOURCE_IRQ,
42 }, {
43 .start = data->dmairq,
44 .end = data->dmairq,
45 .flags = IORESOURCE_IRQ,
46 },
47 };
48
49 return mxs_add_platform_device("mxs-i2c", data->id, res,
50 ARRAY_SIZE(res), NULL, 0);
51}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
new file mode 100644
index 000000000000..680f5a902936
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/devices-common.h>
11
12struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id)
13{
14 struct resource res = {
15 .flags = IORESOURCE_MEM,
16 };
17
18 res.start = iobase + 0x10 + 0x20 * id;
19 res.end = res.start + 0x1f;
20
21 return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0);
22}
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
new file mode 100644
index 000000000000..bf72c9b8dbdd
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c
@@ -0,0 +1,46 @@
1/*
2 * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <asm/sizes.h>
9#include <mach/mx23.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12#include <mach/mxsfb.h>
13
14#ifdef CONFIG_SOC_IMX23
15struct platform_device *__init mx23_add_mxsfb(
16 const struct mxsfb_platform_data *pdata)
17{
18 struct resource res[] = {
19 {
20 .start = MX23_LCDIF_BASE_ADDR,
21 .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1,
22 .flags = IORESOURCE_MEM,
23 },
24 };
25
26 return mxs_add_platform_device_dmamask("imx23-fb", -1,
27 res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
28}
29#endif /* ifdef CONFIG_SOC_IMX23 */
30
31#ifdef CONFIG_SOC_IMX28
32struct platform_device *__init mx28_add_mxsfb(
33 const struct mxsfb_platform_data *pdata)
34{
35 struct resource res[] = {
36 {
37 .start = MX28_LCDIF_BASE_ADDR,
38 .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1,
39 .flags = IORESOURCE_MEM,
40 },
41 };
42
43 return mxs_add_platform_device_dmamask("imx28-fb", -1,
44 res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
45}
46#endif /* ifdef CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
index 61991e4dde44..56fa2ed15222 100644
--- a/arch/arm/mach-mxs/gpio.c
+++ b/arch/arm/mach-mxs/gpio.c
@@ -182,6 +182,7 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
182} 182}
183 183
184static struct irq_chip gpio_irq_chip = { 184static struct irq_chip gpio_irq_chip = {
185 .name = "mxs gpio",
185 .irq_ack = mxs_gpio_ack_irq, 186 .irq_ack = mxs_gpio_ack_irq,
186 .irq_mask = mxs_gpio_mask_irq, 187 .irq_mask = mxs_gpio_mask_irq,
187 .irq_unmask = mxs_gpio_unmask_irq, 188 .irq_unmask = mxs_gpio_unmask_irq,
@@ -289,39 +290,42 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
289 return 0; 290 return 0;
290} 291}
291 292
292#define DEFINE_MXS_GPIO_PORT(soc, _id) \ 293#define MX23_GPIO_BASE MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
294#define MX28_GPIO_BASE MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
295
296#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id) \
293 { \ 297 { \
294 .chip.label = "gpio-" #_id, \ 298 .chip.label = "gpio-" #_id, \
295 .id = _id, \ 299 .id = _id, \
296 .irq = soc ## _INT_GPIO ## _id, \ 300 .irq = _irq, \
297 .base = soc ## _IO_ADDRESS( \ 301 .base = _base, \
298 soc ## _PINCTRL ## _BASE_ADDR), \
299 .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \ 302 .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \
300 } 303 }
301 304
302#define DEFINE_REGISTER_FUNCTION(prefix) \
303int __init prefix ## _register_gpios(void) \
304{ \
305 return mxs_gpio_init(prefix ## _gpio_ports, \
306 ARRAY_SIZE(prefix ## _gpio_ports)); \
307}
308
309#ifdef CONFIG_SOC_IMX23 305#ifdef CONFIG_SOC_IMX23
310static struct mxs_gpio_port mx23_gpio_ports[] = { 306static struct mxs_gpio_port mx23_gpio_ports[] = {
311 DEFINE_MXS_GPIO_PORT(MX23, 0), 307 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
312 DEFINE_MXS_GPIO_PORT(MX23, 1), 308 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
313 DEFINE_MXS_GPIO_PORT(MX23, 2), 309 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
314}; 310};
315DEFINE_REGISTER_FUNCTION(mx23) 311
312int __init mx23_register_gpios(void)
313{
314 return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
315}
316#endif 316#endif
317 317
318#ifdef CONFIG_SOC_IMX28 318#ifdef CONFIG_SOC_IMX28
319static struct mxs_gpio_port mx28_gpio_ports[] = { 319static struct mxs_gpio_port mx28_gpio_ports[] = {
320 DEFINE_MXS_GPIO_PORT(MX28, 0), 320 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
321 DEFINE_MXS_GPIO_PORT(MX28, 1), 321 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
322 DEFINE_MXS_GPIO_PORT(MX28, 2), 322 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
323 DEFINE_MXS_GPIO_PORT(MX28, 3), 323 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
324 DEFINE_MXS_GPIO_PORT(MX28, 4), 324 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
325}; 325};
326DEFINE_REGISTER_FUNCTION(mx28) 326
327int __init mx28_register_gpios(void)
328{
329 return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
330}
327#endif 331#endif
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 59133eb3cc96..635bb5d9a20a 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -13,6 +13,7 @@
13 13
14struct clk; 14struct clk;
15 15
16extern const u32 *mxs_get_ocotp(void);
16extern int mxs_reset_block(void __iomem *); 17extern int mxs_reset_block(void __iomem *);
17extern void mxs_timer_init(struct clk *, int); 18extern void mxs_timer_init(struct clk *, int);
18 19
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 6c3d1a103433..71f24484b044 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -30,6 +30,16 @@ int __init mxs_add_amba_device(const struct amba_device *dev);
30/* duart */ 30/* duart */
31int __init mxs_add_duart(const struct amba_device *dev); 31int __init mxs_add_duart(const struct amba_device *dev);
32 32
33/* auart */
34struct mxs_auart_data {
35 int id;
36 resource_size_t iobase;
37 resource_size_t iosize;
38 resource_size_t irq;
39};
40struct platform_device *__init mxs_add_auart(
41 const struct mxs_auart_data *data);
42
33/* fec */ 43/* fec */
34#include <linux/fec.h> 44#include <linux/fec.h>
35struct mxs_fec_data { 45struct mxs_fec_data {
@@ -41,3 +51,28 @@ struct mxs_fec_data {
41struct platform_device *__init mxs_add_fec( 51struct platform_device *__init mxs_add_fec(
42 const struct mxs_fec_data *data, 52 const struct mxs_fec_data *data,
43 const struct fec_platform_data *pdata); 53 const struct fec_platform_data *pdata);
54
55/* flexcan */
56#include <linux/can/platform/flexcan.h>
57struct mxs_flexcan_data {
58 int id;
59 resource_size_t iobase;
60 resource_size_t iosize;
61 resource_size_t irq;
62};
63struct platform_device *__init mxs_add_flexcan(
64 const struct mxs_flexcan_data *data,
65 const struct flexcan_platform_data *pdata);
66
67/* i2c */
68struct mxs_i2c_data {
69 int id;
70 resource_size_t iobase;
71 resource_size_t errirq;
72 resource_size_t dmairq;
73};
74struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data);
75
76/* pwm */
77struct platform_device *__init mxs_add_mxs_pwm(
78 resource_size_t iobase, int id);
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
index 94e5dd83cdb8..b0190a4822f2 100644
--- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
@@ -254,102 +254,102 @@
254#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) 254#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2)
255 255
256/* MUXSEL_GPIO */ 256/* MUXSEL_GPIO */
257#define MX23_PAD_GPMI_D00__GPO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) 257#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO)
258#define MX23_PAD_GPMI_D01__GPO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) 258#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO)
259#define MX23_PAD_GPMI_D02__GPO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) 259#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO)
260#define MX23_PAD_GPMI_D03__GPO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) 260#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO)
261#define MX23_PAD_GPMI_D04__GPO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) 261#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO)
262#define MX23_PAD_GPMI_D05__GPO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) 262#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO)
263#define MX23_PAD_GPMI_D06__GPO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) 263#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO)
264#define MX23_PAD_GPMI_D07__GPO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) 264#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO)
265#define MX23_PAD_GPMI_D08__GPO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) 265#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO)
266#define MX23_PAD_GPMI_D09__GPO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) 266#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO)
267#define MX23_PAD_GPMI_D10__GPO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) 267#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
268#define MX23_PAD_GPMI_D11__GPO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) 268#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
269#define MX23_PAD_GPMI_D12__GPO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) 269#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
270#define MX23_PAD_GPMI_D13__GPO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) 270#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
271#define MX23_PAD_GPMI_D14__GPO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) 271#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
272#define MX23_PAD_GPMI_D15__GPO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) 272#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
273#define MX23_PAD_GPMI_CLE__GPO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) 273#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
274#define MX23_PAD_GPMI_ALE__GPO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) 274#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
275#define MX23_PAD_GPMI_CE2N__GPO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) 275#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
276#define MX23_PAD_GPMI_RDY0__GPO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) 276#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
277#define MX23_PAD_GPMI_RDY1__GPO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) 277#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
278#define MX23_PAD_GPMI_RDY2__GPO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) 278#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
279#define MX23_PAD_GPMI_RDY3__GPO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) 279#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
280#define MX23_PAD_GPMI_WPN__GPO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) 280#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
281#define MX23_PAD_GPMI_WRN__GPO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) 281#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
282#define MX23_PAD_GPMI_RDN__GPO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) 282#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
283#define MX23_PAD_AUART1_CTS__GPO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) 283#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
284#define MX23_PAD_AUART1_RTS__GPO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) 284#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
285#define MX23_PAD_AUART1_RX__GPO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) 285#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
286#define MX23_PAD_AUART1_TX__GPO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) 286#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
287#define MX23_PAD_I2C_SCL__GPO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) 287#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
288#define MX23_PAD_I2C_SDA__GPO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) 288#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
289 289
290#define MX23_PAD_LCD_D00__GPO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) 290#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO)
291#define MX23_PAD_LCD_D01__GPO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) 291#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO)
292#define MX23_PAD_LCD_D02__GPO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) 292#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO)
293#define MX23_PAD_LCD_D03__GPO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) 293#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO)
294#define MX23_PAD_LCD_D04__GPO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) 294#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO)
295#define MX23_PAD_LCD_D05__GPO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) 295#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO)
296#define MX23_PAD_LCD_D06__GPO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) 296#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO)
297#define MX23_PAD_LCD_D07__GPO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) 297#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO)
298#define MX23_PAD_LCD_D08__GPO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) 298#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO)
299#define MX23_PAD_LCD_D09__GPO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) 299#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO)
300#define MX23_PAD_LCD_D10__GPO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) 300#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
301#define MX23_PAD_LCD_D11__GPO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) 301#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
302#define MX23_PAD_LCD_D12__GPO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) 302#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
303#define MX23_PAD_LCD_D13__GPO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) 303#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
304#define MX23_PAD_LCD_D14__GPO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) 304#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
305#define MX23_PAD_LCD_D15__GPO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) 305#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
306#define MX23_PAD_LCD_D16__GPO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) 306#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
307#define MX23_PAD_LCD_D17__GPO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) 307#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
308#define MX23_PAD_LCD_RESET__GPO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) 308#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
309#define MX23_PAD_LCD_RS__GPO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) 309#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
310#define MX23_PAD_LCD_WR__GPO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) 310#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
311#define MX23_PAD_LCD_CS__GPO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) 311#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
312#define MX23_PAD_LCD_DOTCK__GPO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) 312#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
313#define MX23_PAD_LCD_ENABLE__GPO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) 313#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
314#define MX23_PAD_LCD_HSYNC__GPO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) 314#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
315#define MX23_PAD_LCD_VSYNC__GPO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) 315#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
316#define MX23_PAD_PWM0__GPO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) 316#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
317#define MX23_PAD_PWM1__GPO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) 317#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
318#define MX23_PAD_PWM2__GPO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) 318#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
319#define MX23_PAD_PWM3__GPO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) 319#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
320#define MX23_PAD_PWM4__GPO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) 320#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
321 321
322#define MX23_PAD_SSP1_CMD__GPO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) 322#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO)
323#define MX23_PAD_SSP1_DETECT__GPO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) 323#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO)
324#define MX23_PAD_SSP1_DATA0__GPO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) 324#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO)
325#define MX23_PAD_SSP1_DATA1__GPO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) 325#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO)
326#define MX23_PAD_SSP1_DATA2__GPO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) 326#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO)
327#define MX23_PAD_SSP1_DATA3__GPO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) 327#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO)
328#define MX23_PAD_SSP1_SCK__GPO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) 328#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO)
329#define MX23_PAD_ROTARYA__GPO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) 329#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO)
330#define MX23_PAD_ROTARYB__GPO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) 330#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO)
331#define MX23_PAD_EMI_A00__GPO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) 331#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO)
332#define MX23_PAD_EMI_A01__GPO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) 332#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
333#define MX23_PAD_EMI_A02__GPO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) 333#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
334#define MX23_PAD_EMI_A03__GPO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) 334#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
335#define MX23_PAD_EMI_A04__GPO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) 335#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
336#define MX23_PAD_EMI_A05__GPO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) 336#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
337#define MX23_PAD_EMI_A06__GPO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) 337#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
338#define MX23_PAD_EMI_A07__GPO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) 338#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
339#define MX23_PAD_EMI_A08__GPO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) 339#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
340#define MX23_PAD_EMI_A09__GPO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) 340#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
341#define MX23_PAD_EMI_A10__GPO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) 341#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
342#define MX23_PAD_EMI_A11__GPO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) 342#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
343#define MX23_PAD_EMI_A12__GPO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) 343#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
344#define MX23_PAD_EMI_BA0__GPO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) 344#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
345#define MX23_PAD_EMI_BA1__GPO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) 345#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
346#define MX23_PAD_EMI_CASN__GPO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) 346#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
347#define MX23_PAD_EMI_CE0N__GPO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) 347#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
348#define MX23_PAD_EMI_CE1N__GPO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) 348#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
349#define MX23_PAD_GPMI_CE1N__GPO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) 349#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
350#define MX23_PAD_GPMI_CE0N__GPO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) 350#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
351#define MX23_PAD_EMI_CKE__GPO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) 351#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
352#define MX23_PAD_EMI_RASN__GPO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) 352#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
353#define MX23_PAD_EMI_WEN__GPO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) 353#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
354 354
355#endif /* __MACH_IOMUX_MX23_H__ */ 355#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
index fe558e3c5a9a..7abdf58b8bb7 100644
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ b/arch/arm/mach-mxs/include/mach/iomux.h
@@ -91,6 +91,9 @@ typedef u32 iomux_cfg_t;
91#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ 91#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
92 MXS_PAD_PULL_VALID_MASK) 92 MXS_PAD_PULL_VALID_MASK)
93 93
94/* generic pad control used in most cases */
95#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
96
94#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ 97#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \
95 (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ 98 (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \
96 ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ 99 ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
index 9edd02ec8e30..c0a18c23084a 100644
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -93,7 +93,7 @@
93#define MX23_INT_USB_WAKEUP 12 93#define MX23_INT_USB_WAKEUP 12
94#define MX23_INT_GPMI_DMA 13 94#define MX23_INT_GPMI_DMA 13
95#define MX23_INT_SSP1_DMA 14 95#define MX23_INT_SSP1_DMA 14
96#define MX23_INT_SSP_ERROR 15 96#define MX23_INT_SSP1_ERROR 15
97#define MX23_INT_GPIO0 16 97#define MX23_INT_GPIO0 16
98#define MX23_INT_GPIO1 17 98#define MX23_INT_GPIO1 17
99#define MX23_INT_GPIO2 18 99#define MX23_INT_GPIO2 18
@@ -101,9 +101,9 @@
101#define MX23_INT_SSP2_DMA 20 101#define MX23_INT_SSP2_DMA 20
102#define MX23_INT_ECC8_IRQ 21 102#define MX23_INT_ECC8_IRQ 21
103#define MX23_INT_RTC_ALARM 22 103#define MX23_INT_RTC_ALARM 22
104#define MX23_INT_UARTAPP_TX_DMA 23 104#define MX23_INT_AUART1_TX_DMA 23
105#define MX23_INT_UARTAPP_INTERNAL 24 105#define MX23_INT_AUART1 24
106#define MX23_INT_UARTAPP_RX_DMA 25 106#define MX23_INT_AUART1_RX_DMA 25
107#define MX23_INT_I2C_DMA 26 107#define MX23_INT_I2C_DMA 26
108#define MX23_INT_I2C_ERROR 27 108#define MX23_INT_I2C_ERROR 27
109#define MX23_INT_TIMER0 28 109#define MX23_INT_TIMER0 28
@@ -135,11 +135,35 @@
135#define MX23_INT_DCP 54 135#define MX23_INT_DCP 54
136#define MX23_INT_BCH 56 136#define MX23_INT_BCH 56
137#define MX23_INT_PXP 57 137#define MX23_INT_PXP 57
138#define MX23_INT_UARTAPP2_TX_DMA 58 138#define MX23_INT_AUART2_TX_DMA 58
139#define MX23_INT_UARTAPP2_INTERNAL 59 139#define MX23_INT_AUART2 59
140#define MX23_INT_UARTAPP2_RX_DMA 60 140#define MX23_INT_AUART2_RX_DMA 60
141#define MX23_INT_VDAC_DETECT 61 141#define MX23_INT_VDAC_DETECT 61
142#define MX23_INT_VDD5V_DROOP 64 142#define MX23_INT_VDD5V_DROOP 64
143#define MX23_INT_DCDC4P2_BO 65 143#define MX23_INT_DCDC4P2_BO 65
144 144
145/*
146 * APBH DMA
147 */
148#define MX23_DMA_SSP1 1
149#define MX23_DMA_SSP2 2
150#define MX23_DMA_GPMI0 4
151#define MX23_DMA_GPMI1 5
152#define MX23_DMA_GPMI2 6
153#define MX23_DMA_GPMI3 7
154
155/*
156 * APBX DMA
157 */
158#define MX23_DMA_ADC 0
159#define MX23_DMA_DAC 1
160#define MX23_DMA_SPDIF 2
161#define MX23_DMA_I2C 3
162#define MX23_DMA_SAIF0 4
163#define MX23_DMA_UART0_RX 6
164#define MX23_DMA_UART0_TX 7
165#define MX23_DMA_UART1_RX 8
166#define MX23_DMA_UART1_TX 9
167#define MX23_DMA_SAIF1 10
168
145#endif /* __MACH_MX23_H__ */ 169#endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
index 0716745267ad..75d86118b76a 100644
--- a/arch/arm/mach-mxs/include/mach/mx28.h
+++ b/arch/arm/mach-mxs/include/mach/mx28.h
@@ -163,10 +163,10 @@
163#define MX28_INT_USB0 93 163#define MX28_INT_USB0 93
164#define MX28_INT_USB1_WAKEUP 94 164#define MX28_INT_USB1_WAKEUP 94
165#define MX28_INT_USB0_WAKEUP 95 165#define MX28_INT_USB0_WAKEUP 95
166#define MX28_INT_SSP0 96 166#define MX28_INT_SSP0_ERROR 96
167#define MX28_INT_SSP1 97 167#define MX28_INT_SSP1_ERROR 97
168#define MX28_INT_SSP2 98 168#define MX28_INT_SSP2_ERROR 98
169#define MX28_INT_SSP3 99 169#define MX28_INT_SSP3_ERROR 99
170#define MX28_INT_ENET_SWI 100 170#define MX28_INT_ENET_SWI 100
171#define MX28_INT_ENET_MAC0 101 171#define MX28_INT_ENET_MAC0 101
172#define MX28_INT_ENET_MAC1 102 172#define MX28_INT_ENET_MAC1 102
@@ -185,4 +185,41 @@
185#define MX28_INT_GPIO1 126 185#define MX28_INT_GPIO1 126
186#define MX28_INT_GPIO0 127 186#define MX28_INT_GPIO0 127
187 187
188/*
189 * APBH DMA
190 */
191#define MX28_DMA_SSP0 0
192#define MX28_DMA_SSP1 1
193#define MX28_DMA_SSP2 2
194#define MX28_DMA_SSP3 3
195#define MX28_DMA_GPMI0 4
196#define MX28_DMA_GPMI1 5
197#define MX28_DMA_GPMI2 6
198#define MX28_DMA_GPMI3 7
199#define MX28_DMA_GPMI4 8
200#define MX28_DMA_GPMI5 9
201#define MX28_DMA_GPMI6 10
202#define MX28_DMA_GPMI7 11
203#define MX28_DMA_HSADC 12
204#define MX28_DMA_LCDIF 13
205
206/*
207 * APBX DMA
208 */
209#define MX28_DMA_AUART4_RX 0
210#define MX28_DMA_AUART4_TX 1
211#define MX28_DMA_SPDIF_TX 2
212#define MX28_DMA_SAIF0 4
213#define MX28_DMA_SAIF1 5
214#define MX28_DMA_I2C0 6
215#define MX28_DMA_I2C1 7
216#define MX28_DMA_AUART0_RX 8
217#define MX28_DMA_AUART0_TX 9
218#define MX28_DMA_AUART1_RX 10
219#define MX28_DMA_AUART1_TX 11
220#define MX28_DMA_AUART2_RX 12
221#define MX28_DMA_AUART2_TX 13
222#define MX28_DMA_AUART3_RX 14
223#define MX28_DMA_AUART3_TX 15
224
188#endif /* __MACH_MX28_H__ */ 225#endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index f186c08c2911..35a89dd27242 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -28,8 +28,13 @@
28/* 28/*
29 * MXS CPU types 29 * MXS CPU types
30 */ 30 */
31#define cpu_is_mx23() (machine_is_mx23evk()) 31#define cpu_is_mx23() ( \
32#define cpu_is_mx28() (machine_is_mx28evk()) 32 machine_is_mx23evk() || \
33 0)
34#define cpu_is_mx28() ( \
35 machine_is_mx28evk() || \
36 machine_is_tx28() || \
37 0)
33 38
34/* 39/*
35 * IO addresses common to MXS-based 40 * IO addresses common to MXS-based
diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h
new file mode 100644
index 000000000000..e4d79791515e
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mxsfb.h
@@ -0,0 +1,49 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
14 * MA 02110-1301, USA.
15 */
16
17#ifndef __MACH_FB_H
18#define __MACH_FB_H
19
20#include <linux/fb.h>
21
22#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */
23#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
24#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
25#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
26
27#define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
28#define FB_SYNC_DOTCLK_FAILING_ACT (1 << 7) /* failing/negtive edge sampling */
29
30struct mxsfb_platform_data {
31 struct fb_videomode *mode_list;
32 unsigned mode_count;
33
34 unsigned default_bpp;
35
36 unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */
37 unsigned ld_intf_width; /* refer STMLCDIF_* macros */
38
39 unsigned fb_size; /* Size of the video memory. If zero a
40 * default will be used
41 */
42 unsigned long fb_phys; /* physical address for the video memory. If
43 * zero the framebuffer memory will be dynamically
44 * allocated. If specified,fb_size must also be specified.
45 * fb_phys must be unused by Linux.
46 */
47};
48
49#endif /* __MACH_FB_H */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index a005e76f34f9..f12a1732d8b8 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
63 mxs_duart_base = MX23_DUART_BASE_ADDR; 63 mxs_duart_base = MX23_DUART_BASE_ADDR;
64 break; 64 break;
65 case MACH_TYPE_MX28EVK: 65 case MACH_TYPE_MX28EVK:
66 case MACH_TYPE_TX28:
66 mxs_duart_base = MX28_DUART_BASE_ADDR; 67 mxs_duart_base = MX28_DUART_BASE_ADDR;
67 break; 68 break;
68 default: 69 default:
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index aa0640052f58..a66994f0518f 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -26,17 +26,103 @@
26 26
27#include "devices-mx23.h" 27#include "devices-mx23.h"
28 28
29#define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18)
30#define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28)
31
29static const iomux_cfg_t mx23evk_pads[] __initconst = { 32static const iomux_cfg_t mx23evk_pads[] __initconst = {
30 /* duart */ 33 /* duart */
31 MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA, 34 MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
32 MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA, 35 MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
36
37 /* auart */
38 MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
39 MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
40 MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL,
41 MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL,
42
43 /* mxsfb (lcdif) */
44 MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL,
45 MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL,
46 MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL,
47 MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL,
48 MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL,
49 MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL,
50 MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL,
51 MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL,
52 MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL,
53 MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL,
54 MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
55 MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
56 MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
57 MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
58 MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
59 MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
60 MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
61 MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
62 MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL,
63 MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL,
64 MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL,
65 MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL,
66 MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL,
67 MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL,
68 MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
69 MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
70 MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL,
71 MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
72 /* LCD panel enable */
73 MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
74 /* backlight control */
75 MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
76};
77
78/* mxsfb (lcdif) */
79static struct fb_videomode mx23evk_video_modes[] = {
80 {
81 .name = "Samsung-LMS430HF02",
82 .refresh = 60,
83 .xres = 480,
84 .yres = 272,
85 .pixclock = 108096, /* picosecond (9.2 MHz) */
86 .left_margin = 15,
87 .right_margin = 8,
88 .upper_margin = 12,
89 .lower_margin = 4,
90 .hsync_len = 1,
91 .vsync_len = 1,
92 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
93 FB_SYNC_DOTCLK_FAILING_ACT,
94 },
95};
96
97static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
98 .mode_list = mx23evk_video_modes,
99 .mode_count = ARRAY_SIZE(mx23evk_video_modes),
100 .default_bpp = 32,
101 .ld_intf_width = STMLCDIF_24BIT,
33}; 102};
34 103
35static void __init mx23evk_init(void) 104static void __init mx23evk_init(void)
36{ 105{
106 int ret;
107
37 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); 108 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
38 109
39 mx23_add_duart(); 110 mx23_add_duart();
111 mx23_add_auart0();
112
113 ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
114 if (ret)
115 pr_warn("failed to request gpio lcd-enable: %d\n", ret);
116 else
117 gpio_set_value(MX23EVK_LCD_ENABLE, 1);
118
119 ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
120 if (ret)
121 pr_warn("failed to request gpio bl-enable: %d\n", ret);
122 else
123 gpio_set_value(MX23EVK_BL_ENABLE, 1);
124
125 mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
40} 126}
41 127
42static void __init mx23evk_timer_init(void) 128static void __init mx23evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 8e2c5975001e..08002d02267a 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -28,54 +28,93 @@
28#include "devices-mx28.h" 28#include "devices-mx28.h"
29#include "gpio.h" 29#include "gpio.h"
30 30
31#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
31#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) 32#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15)
33#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18)
34#define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30)
32#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) 35#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
33 36
34static const iomux_cfg_t mx28evk_pads[] __initconst = { 37static const iomux_cfg_t mx28evk_pads[] __initconst = {
35 /* duart */ 38 /* duart */
36 MX28_PAD_PWM0__DUART_RX | 39 MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
37 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 40 MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
38 MX28_PAD_PWM1__DUART_TX |
39 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
40 41
42 /* auart0 */
43 MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
44 MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
45 MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
46 MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
47 /* auart3 */
48 MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
49 MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
50 MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
51 MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
52
53#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
41 /* fec0 */ 54 /* fec0 */
42 MX28_PAD_ENET0_MDC__ENET0_MDC | 55 MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
43 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 56 MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
44 MX28_PAD_ENET0_MDIO__ENET0_MDIO | 57 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
45 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 58 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
46 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | 59 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
47 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 60 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
48 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | 61 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
49 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 62 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
50 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | 63 MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
51 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
52 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN |
53 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
54 MX28_PAD_ENET0_TXD0__ENET0_TXD0 |
55 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
56 MX28_PAD_ENET0_TXD1__ENET0_TXD1 |
57 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
58 MX28_PAD_ENET_CLK__CLKCTRL_ENET |
59 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
60 /* fec1 */ 64 /* fec1 */
61 MX28_PAD_ENET0_CRS__ENET1_RX_EN | 65 MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
62 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 66 MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
63 MX28_PAD_ENET0_RXD2__ENET1_RXD0 | 67 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
64 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 68 MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
65 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | 69 MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
66 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 70 MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
67 MX28_PAD_ENET0_COL__ENET1_TX_EN |
68 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
69 MX28_PAD_ENET0_TXD2__ENET1_TXD0 |
70 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
71 MX28_PAD_ENET0_TXD3__ENET1_TXD1 |
72 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
73 /* phy power line */ 71 /* phy power line */
74 MX28_PAD_SSP1_DATA3__GPIO_2_15 | 72 MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
75 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
76 /* phy reset line */ 73 /* phy reset line */
77 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | 74 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
78 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 75
76 /* flexcan0 */
77 MX28_PAD_GPMI_RDY2__CAN0_TX,
78 MX28_PAD_GPMI_RDY3__CAN0_RX,
79 /* flexcan1 */
80 MX28_PAD_GPMI_CE2N__CAN1_TX,
81 MX28_PAD_GPMI_CE3N__CAN1_RX,
82 /* transceiver power control */
83 MX28_PAD_SSP1_CMD__GPIO_2_13,
84
85 /* mxsfb (lcdif) */
86 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
87 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
88 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
89 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
90 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
91 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
92 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
93 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
94 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
95 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
96 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
97 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
98 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
99 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
100 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
101 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
102 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
103 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
104 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
105 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
106 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
107 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
108 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
109 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
110 MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
111 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
112 MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
113 MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL,
114 /* LCD panel enable */
115 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
116 /* backlight control */
117 MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
79}; 118};
80 119
81/* fec */ 120/* fec */
@@ -119,7 +158,7 @@ static void __init mx28evk_fec_reset(void)
119 gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); 158 gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
120} 159}
121 160
122static struct fec_platform_data mx28_fec_pdata[] = { 161static struct fec_platform_data mx28_fec_pdata[] __initdata = {
123 { 162 {
124 /* fec0 */ 163 /* fec0 */
125 .phy = PHY_INTERFACE_MODE_RMII, 164 .phy = PHY_INTERFACE_MODE_RMII,
@@ -129,15 +168,135 @@ static struct fec_platform_data mx28_fec_pdata[] = {
129 }, 168 },
130}; 169};
131 170
171static int __init mx28evk_fec_get_mac(void)
172{
173 int i;
174 u32 val;
175 const u32 *ocotp = mxs_get_ocotp();
176
177 if (!ocotp)
178 goto error;
179
180 /*
181 * OCOTP only stores the last 4 octets for each mac address,
182 * so hard-code Freescale OUI (00:04:9f) here.
183 */
184 for (i = 0; i < 2; i++) {
185 val = ocotp[i * 4];
186 mx28_fec_pdata[i].mac[0] = 0x00;
187 mx28_fec_pdata[i].mac[1] = 0x04;
188 mx28_fec_pdata[i].mac[2] = 0x9f;
189 mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
190 mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
191 mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
192 }
193
194 return 0;
195
196error:
197 pr_err("%s: timeout when reading fec mac from OCOTP\n", __func__);
198 return -ETIMEDOUT;
199}
200
201/*
202 * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
203 */
204static int flexcan0_en, flexcan1_en;
205
206static void mx28evk_flexcan_switch(void)
207{
208 if (flexcan0_en || flexcan1_en)
209 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
210 else
211 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
212}
213
214static void mx28evk_flexcan0_switch(int enable)
215{
216 flexcan0_en = enable;
217 mx28evk_flexcan_switch();
218}
219
220static void mx28evk_flexcan1_switch(int enable)
221{
222 flexcan1_en = enable;
223 mx28evk_flexcan_switch();
224}
225
226static const struct flexcan_platform_data
227 mx28evk_flexcan_pdata[] __initconst = {
228 {
229 .transceiver_switch = mx28evk_flexcan0_switch,
230 }, {
231 .transceiver_switch = mx28evk_flexcan1_switch,
232 }
233};
234
235/* mxsfb (lcdif) */
236static struct fb_videomode mx28evk_video_modes[] = {
237 {
238 .name = "Seiko-43WVF1G",
239 .refresh = 60,
240 .xres = 800,
241 .yres = 480,
242 .pixclock = 29851, /* picosecond (33.5 MHz) */
243 .left_margin = 89,
244 .right_margin = 164,
245 .upper_margin = 23,
246 .lower_margin = 10,
247 .hsync_len = 10,
248 .vsync_len = 10,
249 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
250 FB_SYNC_DOTCLK_FAILING_ACT,
251 },
252};
253
254static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
255 .mode_list = mx28evk_video_modes,
256 .mode_count = ARRAY_SIZE(mx28evk_video_modes),
257 .default_bpp = 32,
258 .ld_intf_width = STMLCDIF_24BIT,
259};
260
132static void __init mx28evk_init(void) 261static void __init mx28evk_init(void)
133{ 262{
263 int ret;
264
134 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); 265 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
135 266
136 mx28_add_duart(); 267 mx28_add_duart();
268 mx28_add_auart0();
269 mx28_add_auart3();
270
271 if (mx28evk_fec_get_mac())
272 pr_warn("%s: failed on fec mac setup\n", __func__);
137 273
138 mx28evk_fec_reset(); 274 mx28evk_fec_reset();
139 mx28_add_fec(0, &mx28_fec_pdata[0]); 275 mx28_add_fec(0, &mx28_fec_pdata[0]);
140 mx28_add_fec(1, &mx28_fec_pdata[1]); 276 mx28_add_fec(1, &mx28_fec_pdata[1]);
277
278 ret = gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
279 "flexcan-switch");
280 if (ret) {
281 pr_err("failed to request gpio flexcan-switch: %d\n", ret);
282 } else {
283 mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
284 mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
285 }
286
287 ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
288 if (ret)
289 pr_warn("failed to request gpio lcd-enable: %d\n", ret);
290 else
291 gpio_set_value(MX28EVK_LCD_ENABLE, 1);
292
293 ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
294 if (ret)
295 pr_warn("failed to request gpio bl-enable: %d\n", ret);
296 else
297 gpio_set_value(MX28EVK_BL_ENABLE, 1);
298
299 mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
141} 300}
142 301
143static void __init mx28evk_timer_init(void) 302static void __init mx28evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
new file mode 100644
index 000000000000..b65e3719cbc4
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -0,0 +1,183 @@
1/*
2 * Copyright (C) 2010 <LW@KARO-electronics.de>
3 *
4 * based on: mach-mx28_evk.c
5 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation
10 */
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <linux/leds.h>
14#include <linux/platform_device.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/spi_gpio.h>
17#include <linux/i2c.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/time.h>
21
22#include <mach/common.h>
23#include <mach/iomux-mx28.h>
24
25#include "devices-mx28.h"
26#include "module-tx28.h"
27
28#define TX28_STK5_GPIO_LED MXS_GPIO_NR(4, 10)
29
30static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
31 /* LED */
32 MX28_PAD_ENET0_RXD3__GPIO_4_10 |
33 MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL,
34
35 /* framebuffer */
36#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA)
37 MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE,
38 MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE,
39 MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE,
40 MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE,
41 MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE,
42 MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE,
43 MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE,
44 MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE,
45 MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE,
46 MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE,
47 MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE,
48 MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE,
49 MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE,
50 MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE,
51 MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE,
52 MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE,
53 MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE,
54 MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE,
55 MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE,
56 MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE,
57 MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE,
58 MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE,
59 MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE,
60 MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE,
61 MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE,
62 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE,
63 MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE,
64 MX28_PAD_LCD_CS__LCD_CS | LCD_MODE,
65 MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE,
66 MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE,
67 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE,
68 MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE,
69 MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE,
70 MX28_PAD_PWM0__PWM_0 | LCD_MODE,
71
72 /* UART1 */
73 MX28_PAD_AUART0_CTS__DUART_RX,
74 MX28_PAD_AUART0_RTS__DUART_TX,
75 MX28_PAD_AUART0_TX__DUART_RTS,
76 MX28_PAD_AUART0_RX__DUART_CTS,
77
78 /* UART2 */
79 MX28_PAD_AUART1_RX__AUART1_RX,
80 MX28_PAD_AUART1_TX__AUART1_TX,
81 MX28_PAD_AUART1_RTS__AUART1_RTS,
82 MX28_PAD_AUART1_CTS__AUART1_CTS,
83
84 /* CAN */
85 MX28_PAD_GPMI_RDY2__CAN0_TX,
86 MX28_PAD_GPMI_RDY3__CAN0_RX,
87
88 /* I2C */
89 MX28_PAD_I2C0_SCL__I2C0_SCL,
90 MX28_PAD_I2C0_SDA__I2C0_SDA,
91
92 /* TSC2007 */
93 MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
94
95 /* MMC0 */
96 MX28_PAD_SSP0_DATA0__SSP0_D0 |
97 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
98 MX28_PAD_SSP0_DATA1__SSP0_D1 |
99 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
100 MX28_PAD_SSP0_DATA2__SSP0_D2 |
101 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
102 MX28_PAD_SSP0_DATA3__SSP0_D3 |
103 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
104 MX28_PAD_SSP0_DATA4__SSP0_D4 |
105 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
106 MX28_PAD_SSP0_DATA5__SSP0_D5 |
107 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
108 MX28_PAD_SSP0_DATA6__SSP0_D6 |
109 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
110 MX28_PAD_SSP0_DATA7__SSP0_D7 |
111 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
112 MX28_PAD_SSP0_CMD__SSP0_CMD |
113 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
114 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
115 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
116 MX28_PAD_SSP0_SCK__SSP0_SCK |
117 (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
118};
119
120static struct gpio_led tx28_stk5v3_leds[] = {
121 {
122 .name = "GPIO-LED",
123 .default_trigger = "heartbeat",
124 .gpio = TX28_STK5_GPIO_LED,
125 },
126};
127
128static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = {
129 .leds = tx28_stk5v3_leds,
130 .num_leds = ARRAY_SIZE(tx28_stk5v3_leds),
131};
132
133static struct spi_board_info tx28_spi_board_info[] = {
134 {
135 .modalias = "spidev",
136 .max_speed_hz = 20000000,
137 .bus_num = 0,
138 .chip_select = 1,
139 .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT,
140 .mode = SPI_MODE_0,
141 },
142};
143
144static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
145 {
146 I2C_BOARD_INFO("ds1339", 0x68),
147 },
148};
149
150static void __init tx28_stk5v3_init(void)
151{
152 mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
153 ARRAY_SIZE(tx28_stk5v3_pads));
154
155 mx28_add_duart(); /* UART1 */
156 mx28_add_auart(1); /* UART2 */
157
158 tx28_add_fec0();
159 /* spi via ssp will be added when available */
160 spi_register_board_info(tx28_spi_board_info,
161 ARRAY_SIZE(tx28_spi_board_info));
162 mxs_add_platform_device("leds-gpio", 0, NULL, 0,
163 &tx28_stk5v3_led_data, sizeof(tx28_stk5v3_led_data));
164 mx28_add_mxs_i2c(0);
165 i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
166 ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
167}
168
169static void __init tx28_timer_init(void)
170{
171 mx28_clocks_init();
172}
173
174static struct sys_timer tx28_timer = {
175 .init = tx28_timer_init,
176};
177
178MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
179 .map_io = mx28_map_io,
180 .init_irq = mx28_init_irq,
181 .init_machine = tx28_stk5v3_init,
182 .timer = &tx28_timer,
183MACHINE_END
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
new file mode 100644
index 000000000000..fa0b154da67b
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.c
@@ -0,0 +1,131 @@
1/*
2 * Copyright (C) 2010 <LW@KARO-electronics.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#include <linux/delay.h>
10#include <linux/fec.h>
11#include <linux/gpio.h>
12
13#include <mach/iomux-mx28.h>
14#include "../devices-mx28.h"
15
16#include "module-tx28.h"
17
18#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29)
19#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
20
21static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
22 /* PHY POWER */
23 MX28_PAD_PWM4__GPIO_3_29 |
24 MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
25 /* PHY RESET */
26 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
27 MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
28 /* Mode strap pins 0-2 */
29 MX28_PAD_ENET0_RXD0__GPIO_4_3 |
30 MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
31 MX28_PAD_ENET0_RXD1__GPIO_4_4 |
32 MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
33 MX28_PAD_ENET0_RX_EN__GPIO_4_2 |
34 MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
35 /* nINT */
36 MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
37 MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
38
39 MX28_PAD_ENET0_MDC__GPIO_4_0,
40 MX28_PAD_ENET0_MDIO__GPIO_4_1,
41 MX28_PAD_ENET0_TX_EN__GPIO_4_6,
42 MX28_PAD_ENET0_TXD0__GPIO_4_7,
43 MX28_PAD_ENET0_TXD1__GPIO_4_8,
44 MX28_PAD_ENET_CLK__GPIO_4_16,
45};
46
47#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
48static const iomux_cfg_t tx28_fec_pads[] __initconst = {
49 MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
50 MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
51 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
52 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE,
53 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE,
54 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE,
55 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE,
56 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE,
57 MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
58};
59
60static const struct fec_platform_data tx28_fec_data __initconst = {
61 .phy = PHY_INTERFACE_MODE_RMII,
62};
63
64int __init tx28_add_fec0(void)
65{
66 int i, ret;
67
68 pr_debug("%s: Switching FEC PHY power off\n", __func__);
69 ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads,
70 ARRAY_SIZE(tx28_fec_gpio_pads));
71 for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) {
72 unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
73 PAD_PIN(tx28_fec_gpio_pads[i]));
74
75 ret = gpio_request(gpio, "FEC");
76 if (ret) {
77 pr_err("Failed to request GPIO_%d_%d: %d\n",
78 PAD_BANK(tx28_fec_gpio_pads[i]),
79 PAD_PIN(tx28_fec_gpio_pads[i]), ret);
80 goto free_gpios;
81 }
82 ret = gpio_direction_output(gpio, 0);
83 if (ret) {
84 pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n",
85 gpio / 32 + 1, gpio % 32, ret);
86 goto free_gpios;
87 }
88 }
89
90 /* Power up fec phy */
91 pr_debug("%s: Switching FEC PHY power on\n", __func__);
92 ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1);
93 if (ret) {
94 pr_err("Failed to power on PHY: %d\n", ret);
95 goto free_gpios;
96 }
97 mdelay(26); /* 25ms according to data sheet */
98
99 /* nINT */
100 gpio_direction_input(MXS_GPIO_NR(4, 5));
101 /* Mode strap pins */
102 gpio_direction_output(MXS_GPIO_NR(4, 2), 1);
103 gpio_direction_output(MXS_GPIO_NR(4, 3), 1);
104 gpio_direction_output(MXS_GPIO_NR(4, 4), 1);
105
106 udelay(100); /* minimum assertion time for nRST */
107
108 pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
109 gpio_set_value(TX28_FEC_PHY_RESET, 1);
110
111 ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads,
112 ARRAY_SIZE(tx28_fec_pads));
113 if (ret) {
114 pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
115 __func__, ret);
116 goto free_gpios;
117 }
118 pr_debug("%s: Registering FEC device\n", __func__);
119 mx28_add_fec(0, &tx28_fec_data);
120 return 0;
121
122free_gpios:
123 while (--i >= 0) {
124 unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
125 PAD_PIN(tx28_fec_gpio_pads[i]));
126
127 gpio_free(gpio);
128 }
129
130 return ret;
131}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
new file mode 100644
index 000000000000..df9e1b6e81bf
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.h
@@ -0,0 +1,9 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9int __init tx28_add_fec0(void);
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
new file mode 100644
index 000000000000..65157a35dbba
--- /dev/null
+++ b/arch/arm/mach-mxs/ocotp.c
@@ -0,0 +1,90 @@
1/*
2 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/mutex.h>
18
19#include <mach/mxs.h>
20
21#define OCOTP_WORD_OFFSET 0x20
22#define OCOTP_WORD_COUNT 0x20
23
24#define BM_OCOTP_CTRL_BUSY (1 << 8)
25#define BM_OCOTP_CTRL_ERROR (1 << 9)
26#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
27
28static DEFINE_MUTEX(ocotp_mutex);
29static u32 ocotp_words[OCOTP_WORD_COUNT];
30
31const u32 *mxs_get_ocotp(void)
32{
33 void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
34 int timeout = 0x400;
35 size_t i;
36 static int once = 0;
37
38 if (once)
39 return ocotp_words;
40
41 mutex_lock(&ocotp_mutex);
42
43 /*
44 * clk_enable(hbus_clk) for ocotp can be skipped
45 * as it must be on when system is running.
46 */
47
48 /* try to clear ERROR bit */
49 __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
50
51 /* check both BUSY and ERROR cleared */
52 while ((__raw_readl(ocotp_base) &
53 (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
54 cpu_relax();
55
56 if (unlikely(!timeout))
57 goto error_unlock;
58
59 /* open OCOTP banks for read */
60 __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
61
62 /* approximately wait 32 hclk cycles */
63 udelay(1);
64
65 /* poll BUSY bit becoming cleared */
66 timeout = 0x400;
67 while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
68 cpu_relax();
69
70 if (unlikely(!timeout))
71 goto error_unlock;
72
73 for (i = 0; i < OCOTP_WORD_COUNT; i++)
74 ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
75 i * 0x10);
76
77 /* close banks for power saving */
78 __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
79
80 once = 1;
81
82 mutex_unlock(&ocotp_mutex);
83
84 return ocotp_words;
85
86error_unlock:
87 mutex_unlock(&ocotp_mutex);
88 pr_err("%s: timeout in reading OCOTP\n", __func__);
89 return NULL;
90}
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
new file mode 100644
index 000000000000..fb042da29bda
--- /dev/null
+++ b/arch/arm/mach-mxs/pm.c
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/suspend.h>
17#include <linux/io.h>
18#include <mach/system.h>
19
20static int mxs_suspend_enter(suspend_state_t state)
21{
22 switch (state) {
23 case PM_SUSPEND_MEM:
24 arch_idle();
25 break;
26
27 default:
28 return -EINVAL;
29 }
30 return 0;
31}
32
33static struct platform_suspend_ops mxs_suspend_ops = {
34 .enter = mxs_suspend_enter,
35 .valid = suspend_valid_only_mem,
36};
37
38static int __init mxs_pm_init(void)
39{
40 suspend_set_ops(&mxs_suspend_ops);
41 return 0;
42}
43device_initcall(mxs_pm_init);
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
index dbc04747b691..0ea5c9d0e2b2 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx23.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -33,10 +33,6 @@
33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) 33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) 34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
35 35
36#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30
37#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000
38#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
39 (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
40#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 36#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
41#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 37#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
42#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ 38#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
@@ -45,10 +41,6 @@
45#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 41#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
46#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 42#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
47#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 43#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
48#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26
49#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000
50#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \
51 (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
52#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 44#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
53#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 45#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
54#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ 46#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
@@ -57,10 +49,6 @@
57#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 49#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
58#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 50#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
59#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 51#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
60#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22
61#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000
62#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \
63 (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
64#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 52#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
65#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 53#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
66#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ 54#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
@@ -69,23 +57,13 @@
69#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 57#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
70#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 58#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
71#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 59#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
72#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000
73#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 60#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
74#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000
75#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 61#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
76#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0
77#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF
78#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \
79 (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
80 62
81#define HW_CLKCTRL_PLLCTRL1 (0x00000010) 63#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
82 64
83#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 65#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
84#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 66#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
85#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16
86#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000
87#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \
88 (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
89#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 67#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
90#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF 68#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
91#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ 69#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
@@ -96,29 +74,15 @@
96#define HW_CLKCTRL_CPU_CLR (0x00000028) 74#define HW_CLKCTRL_CPU_CLR (0x00000028)
97#define HW_CLKCTRL_CPU_TOG (0x0000002c) 75#define HW_CLKCTRL_CPU_TOG (0x0000002c)
98 76
99#define BP_CLKCTRL_CPU_RSRVD5 30
100#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
101#define BF_CLKCTRL_CPU_RSRVD5(v) \
102 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
103#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 77#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
104#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 78#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
105#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
106#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 79#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
107#define BP_CLKCTRL_CPU_DIV_XTAL 16 80#define BP_CLKCTRL_CPU_DIV_XTAL 16
108#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 81#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
109#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ 82#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
110 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) 83 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
111#define BP_CLKCTRL_CPU_RSRVD3 13
112#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
113#define BF_CLKCTRL_CPU_RSRVD3(v) \
114 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
115#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 84#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
116#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
117#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 85#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
118#define BP_CLKCTRL_CPU_RSRVD1 6
119#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
120#define BF_CLKCTRL_CPU_RSRVD1(v) \
121 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
122#define BP_CLKCTRL_CPU_DIV_CPU 0 86#define BP_CLKCTRL_CPU_DIV_CPU 0
123#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 87#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
124#define BF_CLKCTRL_CPU_DIV_CPU(v) \ 88#define BF_CLKCTRL_CPU_DIV_CPU(v) \
@@ -129,10 +93,6 @@
129#define HW_CLKCTRL_HBUS_CLR (0x00000038) 93#define HW_CLKCTRL_HBUS_CLR (0x00000038)
130#define HW_CLKCTRL_HBUS_TOG (0x0000003c) 94#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
131 95
132#define BP_CLKCTRL_HBUS_RSRVD4 30
133#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000
134#define BF_CLKCTRL_HBUS_RSRVD4(v) \
135 (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
136#define BM_CLKCTRL_HBUS_BUSY 0x20000000 96#define BM_CLKCTRL_HBUS_BUSY 0x20000000
137#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 97#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
138#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 98#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
@@ -143,7 +103,6 @@
143#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 103#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
144#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 104#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
145#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 105#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
146#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000
147#define BP_CLKCTRL_HBUS_SLOW_DIV 16 106#define BP_CLKCTRL_HBUS_SLOW_DIV 16
148#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 107#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
149#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ 108#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
@@ -154,10 +113,6 @@
154#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 113#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
155#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 114#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
156#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 115#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
157#define BP_CLKCTRL_HBUS_RSRVD1 6
158#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
159#define BF_CLKCTRL_HBUS_RSRVD1(v) \
160 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
161#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 116#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
162#define BP_CLKCTRL_HBUS_DIV 0 117#define BP_CLKCTRL_HBUS_DIV 0
163#define BM_CLKCTRL_HBUS_DIV 0x0000001F 118#define BM_CLKCTRL_HBUS_DIV 0x0000001F
@@ -167,10 +122,6 @@
167#define HW_CLKCTRL_XBUS (0x00000040) 122#define HW_CLKCTRL_XBUS (0x00000040)
168 123
169#define BM_CLKCTRL_XBUS_BUSY 0x80000000 124#define BM_CLKCTRL_XBUS_BUSY 0x80000000
170#define BP_CLKCTRL_XBUS_RSRVD1 11
171#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800
172#define BF_CLKCTRL_XBUS_RSRVD1(v) \
173 (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
174#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 125#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
175#define BP_CLKCTRL_XBUS_DIV 0 126#define BP_CLKCTRL_XBUS_DIV 0
176#define BM_CLKCTRL_XBUS_DIV 0x000003FF 127#define BM_CLKCTRL_XBUS_DIV 0x000003FF
@@ -192,10 +143,6 @@
192#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 143#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
193#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 144#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
194#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 145#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
195#define BP_CLKCTRL_XTAL_RSRVD1 2
196#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
197#define BF_CLKCTRL_XTAL_RSRVD1(v) \
198 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
199#define BP_CLKCTRL_XTAL_DIV_UART 0 146#define BP_CLKCTRL_XTAL_DIV_UART 0
200#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 147#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
201#define BF_CLKCTRL_XTAL_DIV_UART(v) \ 148#define BF_CLKCTRL_XTAL_DIV_UART(v) \
@@ -205,12 +152,7 @@
205 152
206#define BP_CLKCTRL_PIX_CLKGATE 31 153#define BP_CLKCTRL_PIX_CLKGATE 31
207#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 154#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
208#define BM_CLKCTRL_PIX_RSRVD2 0x40000000
209#define BM_CLKCTRL_PIX_BUSY 0x20000000 155#define BM_CLKCTRL_PIX_BUSY 0x20000000
210#define BP_CLKCTRL_PIX_RSRVD1 13
211#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000
212#define BF_CLKCTRL_PIX_RSRVD1(v) \
213 (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
214#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 156#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
215#define BP_CLKCTRL_PIX_DIV 0 157#define BP_CLKCTRL_PIX_DIV 0
216#define BM_CLKCTRL_PIX_DIV 0x00000FFF 158#define BM_CLKCTRL_PIX_DIV 0x00000FFF
@@ -221,12 +163,7 @@
221 163
222#define BP_CLKCTRL_SSP_CLKGATE 31 164#define BP_CLKCTRL_SSP_CLKGATE 31
223#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 165#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
224#define BM_CLKCTRL_SSP_RSRVD2 0x40000000
225#define BM_CLKCTRL_SSP_BUSY 0x20000000 166#define BM_CLKCTRL_SSP_BUSY 0x20000000
226#define BP_CLKCTRL_SSP_RSRVD1 10
227#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00
228#define BF_CLKCTRL_SSP_RSRVD1(v) \
229 (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
230#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 167#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
231#define BP_CLKCTRL_SSP_DIV 0 168#define BP_CLKCTRL_SSP_DIV 0
232#define BM_CLKCTRL_SSP_DIV 0x000001FF 169#define BM_CLKCTRL_SSP_DIV 0x000001FF
@@ -237,12 +174,7 @@
237 174
238#define BP_CLKCTRL_GPMI_CLKGATE 31 175#define BP_CLKCTRL_GPMI_CLKGATE 31
239#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 176#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
240#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
241#define BM_CLKCTRL_GPMI_BUSY 0x20000000 177#define BM_CLKCTRL_GPMI_BUSY 0x20000000
242#define BP_CLKCTRL_GPMI_RSRVD1 11
243#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
244#define BF_CLKCTRL_GPMI_RSRVD1(v) \
245 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
246#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 178#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
247#define BP_CLKCTRL_GPMI_DIV 0 179#define BP_CLKCTRL_GPMI_DIV 0
248#define BM_CLKCTRL_GPMI_DIV 0x000003FF 180#define BM_CLKCTRL_GPMI_DIV 0x000003FF
@@ -252,10 +184,6 @@
252#define HW_CLKCTRL_SPDIF (0x00000090) 184#define HW_CLKCTRL_SPDIF (0x00000090)
253 185
254#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 186#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
255#define BP_CLKCTRL_SPDIF_RSRVD 0
256#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
257#define BF_CLKCTRL_SPDIF_RSRVD(v) \
258 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
259 187
260#define HW_CLKCTRL_EMI (0x000000a0) 188#define HW_CLKCTRL_EMI (0x000000a0)
261 189
@@ -266,24 +194,12 @@
266#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 194#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
267#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 195#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
268#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 196#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
269#define BP_CLKCTRL_EMI_RSRVD3 18
270#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
271#define BF_CLKCTRL_EMI_RSRVD3(v) \
272 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
273#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 197#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
274#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 198#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
275#define BP_CLKCTRL_EMI_RSRVD2 12
276#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
277#define BF_CLKCTRL_EMI_RSRVD2(v) \
278 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
279#define BP_CLKCTRL_EMI_DIV_XTAL 8 199#define BP_CLKCTRL_EMI_DIV_XTAL 8
280#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 200#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
281#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ 201#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
282 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) 202 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
283#define BP_CLKCTRL_EMI_RSRVD1 6
284#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
285#define BF_CLKCTRL_EMI_RSRVD1(v) \
286 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
287#define BP_CLKCTRL_EMI_DIV_EMI 0 203#define BP_CLKCTRL_EMI_DIV_EMI 0
288#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F 204#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
289#define BF_CLKCTRL_EMI_DIV_EMI(v) \ 205#define BF_CLKCTRL_EMI_DIV_EMI(v) \
@@ -292,22 +208,13 @@
292#define HW_CLKCTRL_IR (0x000000b0) 208#define HW_CLKCTRL_IR (0x000000b0)
293 209
294#define BM_CLKCTRL_IR_CLKGATE 0x80000000 210#define BM_CLKCTRL_IR_CLKGATE 0x80000000
295#define BM_CLKCTRL_IR_RSRVD3 0x40000000
296#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 211#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
297#define BM_CLKCTRL_IR_IR_BUSY 0x10000000 212#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
298#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 213#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
299#define BP_CLKCTRL_IR_RSRVD2 25
300#define BM_CLKCTRL_IR_RSRVD2 0x06000000
301#define BF_CLKCTRL_IR_RSRVD2(v) \
302 (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
303#define BP_CLKCTRL_IR_IROV_DIV 16 214#define BP_CLKCTRL_IR_IROV_DIV 16
304#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 215#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
305#define BF_CLKCTRL_IR_IROV_DIV(v) \ 216#define BF_CLKCTRL_IR_IROV_DIV(v) \
306 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) 217 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
307#define BP_CLKCTRL_IR_RSRVD1 10
308#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00
309#define BF_CLKCTRL_IR_RSRVD1(v) \
310 (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
311#define BP_CLKCTRL_IR_IR_DIV 0 218#define BP_CLKCTRL_IR_IR_DIV 0
312#define BM_CLKCTRL_IR_IR_DIV 0x000003FF 219#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
313#define BF_CLKCTRL_IR_IR_DIV(v) \ 220#define BF_CLKCTRL_IR_IR_DIV(v) \
@@ -316,12 +223,7 @@
316#define HW_CLKCTRL_SAIF (0x000000c0) 223#define HW_CLKCTRL_SAIF (0x000000c0)
317 224
318#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 225#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
319#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000
320#define BM_CLKCTRL_SAIF_BUSY 0x20000000 226#define BM_CLKCTRL_SAIF_BUSY 0x20000000
321#define BP_CLKCTRL_SAIF_RSRVD1 17
322#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000
323#define BF_CLKCTRL_SAIF_RSRVD1(v) \
324 (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
325#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 227#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
326#define BP_CLKCTRL_SAIF_DIV 0 228#define BP_CLKCTRL_SAIF_DIV 0
327#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF 229#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
@@ -332,20 +234,11 @@
332 234
333#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 235#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
334#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 236#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
335#define BP_CLKCTRL_TV_RSRVD 0
336#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF
337#define BF_CLKCTRL_TV_RSRVD(v) \
338 (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
339 237
340#define HW_CLKCTRL_ETM (0x000000e0) 238#define HW_CLKCTRL_ETM (0x000000e0)
341 239
342#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 240#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
343#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
344#define BM_CLKCTRL_ETM_BUSY 0x20000000 241#define BM_CLKCTRL_ETM_BUSY 0x20000000
345#define BP_CLKCTRL_ETM_RSRVD1 7
346#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80
347#define BF_CLKCTRL_ETM_RSRVD1(v) \
348 (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
349#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 242#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
350#define BP_CLKCTRL_ETM_DIV 0 243#define BP_CLKCTRL_ETM_DIV 0
351#define BM_CLKCTRL_ETM_DIV 0x0000003F 244#define BM_CLKCTRL_ETM_DIV 0x0000003F
@@ -393,36 +286,23 @@
393 286
394#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 287#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
395#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 288#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
396#define BP_CLKCTRL_FRAC1_RSRVD1 0
397#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
398#define BF_CLKCTRL_FRAC1_RSRVD1(v) \
399 (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
400 289
401#define HW_CLKCTRL_CLKSEQ (0x00000110) 290#define HW_CLKCTRL_CLKSEQ (0x00000110)
402#define HW_CLKCTRL_CLKSEQ_SET (0x00000114) 291#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
403#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) 292#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
404#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) 293#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
405 294
406#define BP_CLKCTRL_CLKSEQ_RSRVD1 9
407#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00
408#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
409 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
410#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 295#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
411#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 296#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
412#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 297#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
413#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 298#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
414#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 299#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
415#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 300#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
416#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004
417#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 301#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
418#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 302#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
419 303
420#define HW_CLKCTRL_RESET (0x00000120) 304#define HW_CLKCTRL_RESET (0x00000120)
421 305
422#define BP_CLKCTRL_RESET_RSRVD 2
423#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC
424#define BF_CLKCTRL_RESET_RSRVD(v) \
425 (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
426#define BM_CLKCTRL_RESET_CHIP 0x00000002 306#define BM_CLKCTRL_RESET_CHIP 0x00000002
427#define BM_CLKCTRL_RESET_DIG 0x00000001 307#define BM_CLKCTRL_RESET_DIG 0x00000001
428 308
@@ -432,10 +312,6 @@
432#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 312#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
433#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ 313#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
434 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) 314 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
435#define BP_CLKCTRL_STATUS_RSRVD 0
436#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
437#define BF_CLKCTRL_STATUS_RSRVD(v) \
438 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
439 315
440#define HW_CLKCTRL_VERSION (0x00000140) 316#define HW_CLKCTRL_VERSION (0x00000140)
441 317
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
index 661df18755f7..7d1b061d7943 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
@@ -31,10 +31,6 @@
31#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) 31#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
32#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) 32#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
33 33
34#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30
35#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000
36#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
37 (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
38#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 34#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
39#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 35#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
40#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ 36#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
@@ -43,10 +39,6 @@
43#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 39#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
44#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 40#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
45#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 41#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
46#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26
47#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000
48#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \
49 (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
50#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 42#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
51#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 43#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
52#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ 44#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
@@ -55,10 +47,6 @@
55#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 47#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
56#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 48#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
57#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 49#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
58#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22
59#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000
60#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \
61 (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
62#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 50#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
63#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 51#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
64#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ 52#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
@@ -67,22 +55,13 @@
67#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 55#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
68#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 56#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
69#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 57#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
70#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000
71#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 58#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
72#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 59#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
73#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0
74#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF
75#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \
76 (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
77 60
78#define HW_CLKCTRL_PLL0CTRL1 (0x00000010) 61#define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
79 62
80#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 63#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
81#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 64#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
82#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16
83#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000
84#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \
85 (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
86#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 65#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
87#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF 66#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
88#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ 67#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
@@ -94,7 +73,6 @@
94#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) 73#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
95 74
96#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 75#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
97#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000
98#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 76#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
99#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 77#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
100#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ 78#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
@@ -103,10 +81,6 @@
103#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 81#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
104#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 82#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
105#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 83#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
106#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26
107#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000
108#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \
109 (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
110#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 84#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
111#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 85#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
112#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ 86#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
@@ -115,10 +89,6 @@
115#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 89#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
116#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 90#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
117#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 91#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
118#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22
119#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000
120#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \
121 (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
122#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 92#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
123#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 93#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
124#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ 94#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
@@ -127,22 +97,13 @@
127#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 97#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
128#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 98#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
129#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 99#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
130#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000
131#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 100#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
132#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 101#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
133#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0
134#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF
135#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \
136 (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
137 102
138#define HW_CLKCTRL_PLL1CTRL1 (0x00000030) 103#define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
139 104
140#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 105#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
141#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 106#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
142#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16
143#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000
144#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \
145 (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
146#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 107#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
147#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF 108#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
148#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ 109#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
@@ -154,51 +115,31 @@
154#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) 115#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
155 116
156#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 117#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
157#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000
158#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 118#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
159#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 119#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
160#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ 120#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
161 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) 121 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
162#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000
163#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 122#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
164#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 123#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
165#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 124#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
166#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ 125#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
167 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) 126 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
168#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 127#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
169#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0
170#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF
171#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \
172 (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
173 128
174#define HW_CLKCTRL_CPU (0x00000050) 129#define HW_CLKCTRL_CPU (0x00000050)
175#define HW_CLKCTRL_CPU_SET (0x00000054) 130#define HW_CLKCTRL_CPU_SET (0x00000054)
176#define HW_CLKCTRL_CPU_CLR (0x00000058) 131#define HW_CLKCTRL_CPU_CLR (0x00000058)
177#define HW_CLKCTRL_CPU_TOG (0x0000005c) 132#define HW_CLKCTRL_CPU_TOG (0x0000005c)
178 133
179#define BP_CLKCTRL_CPU_RSRVD5 30
180#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
181#define BF_CLKCTRL_CPU_RSRVD5(v) \
182 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
183#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 134#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
184#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 135#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
185#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
186#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 136#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
187#define BP_CLKCTRL_CPU_DIV_XTAL 16 137#define BP_CLKCTRL_CPU_DIV_XTAL 16
188#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 138#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
189#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ 139#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
190 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) 140 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
191#define BP_CLKCTRL_CPU_RSRVD3 13
192#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
193#define BF_CLKCTRL_CPU_RSRVD3(v) \
194 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
195#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 141#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
196#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
197#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 142#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
198#define BP_CLKCTRL_CPU_RSRVD1 6
199#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
200#define BF_CLKCTRL_CPU_RSRVD1(v) \
201 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
202#define BP_CLKCTRL_CPU_DIV_CPU 0 143#define BP_CLKCTRL_CPU_DIV_CPU 0
203#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 144#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
204#define BF_CLKCTRL_CPU_DIV_CPU(v) \ 145#define BF_CLKCTRL_CPU_DIV_CPU(v) \
@@ -212,7 +153,6 @@
212#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 153#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
213#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 154#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
214#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 155#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
215#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000
216#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 156#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
217#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 157#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
218#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 158#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
@@ -232,10 +172,6 @@
232#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 172#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
233#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 173#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
234#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 174#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
235#define BP_CLKCTRL_HBUS_RSRVD1 6
236#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
237#define BF_CLKCTRL_HBUS_RSRVD1(v) \
238 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
239#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 175#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
240#define BP_CLKCTRL_HBUS_DIV 0 176#define BP_CLKCTRL_HBUS_DIV 0
241#define BM_CLKCTRL_HBUS_DIV 0x0000001F 177#define BM_CLKCTRL_HBUS_DIV 0x0000001F
@@ -245,10 +181,6 @@
245#define HW_CLKCTRL_XBUS (0x00000070) 181#define HW_CLKCTRL_XBUS (0x00000070)
246 182
247#define BM_CLKCTRL_XBUS_BUSY 0x80000000 183#define BM_CLKCTRL_XBUS_BUSY 0x80000000
248#define BP_CLKCTRL_XBUS_RSRVD1 12
249#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000
250#define BF_CLKCTRL_XBUS_RSRVD1(v) \
251 (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
252#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 184#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
253#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 185#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
254#define BP_CLKCTRL_XBUS_DIV 0 186#define BP_CLKCTRL_XBUS_DIV 0
@@ -263,19 +195,10 @@
263 195
264#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 196#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
265#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 197#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
266#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000
267#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 198#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
268#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 199#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
269#define BP_CLKCTRL_XTAL_RSRVD2 27
270#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000
271#define BF_CLKCTRL_XTAL_RSRVD2(v) \
272 (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
273#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 200#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
274#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 201#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
275#define BP_CLKCTRL_XTAL_RSRVD1 2
276#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
277#define BF_CLKCTRL_XTAL_RSRVD1(v) \
278 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
279#define BP_CLKCTRL_XTAL_DIV_UART 0 202#define BP_CLKCTRL_XTAL_DIV_UART 0
280#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 203#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
281#define BF_CLKCTRL_XTAL_DIV_UART(v) \ 204#define BF_CLKCTRL_XTAL_DIV_UART(v) \
@@ -285,12 +208,7 @@
285 208
286#define BP_CLKCTRL_SSP0_CLKGATE 31 209#define BP_CLKCTRL_SSP0_CLKGATE 31
287#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 210#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
288#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000
289#define BM_CLKCTRL_SSP0_BUSY 0x20000000 211#define BM_CLKCTRL_SSP0_BUSY 0x20000000
290#define BP_CLKCTRL_SSP0_RSRVD1 10
291#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00
292#define BF_CLKCTRL_SSP0_RSRVD1(v) \
293 (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
294#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 212#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
295#define BP_CLKCTRL_SSP0_DIV 0 213#define BP_CLKCTRL_SSP0_DIV 0
296#define BM_CLKCTRL_SSP0_DIV 0x000001FF 214#define BM_CLKCTRL_SSP0_DIV 0x000001FF
@@ -301,12 +219,7 @@
301 219
302#define BP_CLKCTRL_SSP1_CLKGATE 31 220#define BP_CLKCTRL_SSP1_CLKGATE 31
303#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 221#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
304#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000
305#define BM_CLKCTRL_SSP1_BUSY 0x20000000 222#define BM_CLKCTRL_SSP1_BUSY 0x20000000
306#define BP_CLKCTRL_SSP1_RSRVD1 10
307#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00
308#define BF_CLKCTRL_SSP1_RSRVD1(v) \
309 (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
310#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 223#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
311#define BP_CLKCTRL_SSP1_DIV 0 224#define BP_CLKCTRL_SSP1_DIV 0
312#define BM_CLKCTRL_SSP1_DIV 0x000001FF 225#define BM_CLKCTRL_SSP1_DIV 0x000001FF
@@ -317,12 +230,7 @@
317 230
318#define BP_CLKCTRL_SSP2_CLKGATE 31 231#define BP_CLKCTRL_SSP2_CLKGATE 31
319#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 232#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
320#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000
321#define BM_CLKCTRL_SSP2_BUSY 0x20000000 233#define BM_CLKCTRL_SSP2_BUSY 0x20000000
322#define BP_CLKCTRL_SSP2_RSRVD1 10
323#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00
324#define BF_CLKCTRL_SSP2_RSRVD1(v) \
325 (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
326#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 234#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
327#define BP_CLKCTRL_SSP2_DIV 0 235#define BP_CLKCTRL_SSP2_DIV 0
328#define BM_CLKCTRL_SSP2_DIV 0x000001FF 236#define BM_CLKCTRL_SSP2_DIV 0x000001FF
@@ -333,12 +241,7 @@
333 241
334#define BP_CLKCTRL_SSP3_CLKGATE 31 242#define BP_CLKCTRL_SSP3_CLKGATE 31
335#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 243#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
336#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000
337#define BM_CLKCTRL_SSP3_BUSY 0x20000000 244#define BM_CLKCTRL_SSP3_BUSY 0x20000000
338#define BP_CLKCTRL_SSP3_RSRVD1 10
339#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00
340#define BF_CLKCTRL_SSP3_RSRVD1(v) \
341 (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
342#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 245#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
343#define BP_CLKCTRL_SSP3_DIV 0 246#define BP_CLKCTRL_SSP3_DIV 0
344#define BM_CLKCTRL_SSP3_DIV 0x000001FF 247#define BM_CLKCTRL_SSP3_DIV 0x000001FF
@@ -349,12 +252,7 @@
349 252
350#define BP_CLKCTRL_GPMI_CLKGATE 31 253#define BP_CLKCTRL_GPMI_CLKGATE 31
351#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 254#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
352#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
353#define BM_CLKCTRL_GPMI_BUSY 0x20000000 255#define BM_CLKCTRL_GPMI_BUSY 0x20000000
354#define BP_CLKCTRL_GPMI_RSRVD1 11
355#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
356#define BF_CLKCTRL_GPMI_RSRVD1(v) \
357 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
358#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 256#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
359#define BP_CLKCTRL_GPMI_DIV 0 257#define BP_CLKCTRL_GPMI_DIV 0
360#define BM_CLKCTRL_GPMI_DIV 0x000003FF 258#define BM_CLKCTRL_GPMI_DIV 0x000003FF
@@ -365,10 +263,6 @@
365 263
366#define BP_CLKCTRL_SPDIF_CLKGATE 31 264#define BP_CLKCTRL_SPDIF_CLKGATE 31
367#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 265#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
368#define BP_CLKCTRL_SPDIF_RSRVD 0
369#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
370#define BF_CLKCTRL_SPDIF_RSRVD(v) \
371 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
372 266
373#define HW_CLKCTRL_EMI (0x000000f0) 267#define HW_CLKCTRL_EMI (0x000000f0)
374 268
@@ -379,24 +273,12 @@
379#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 273#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
380#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 274#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
381#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 275#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
382#define BP_CLKCTRL_EMI_RSRVD3 18
383#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
384#define BF_CLKCTRL_EMI_RSRVD3(v) \
385 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
386#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 276#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
387#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 277#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
388#define BP_CLKCTRL_EMI_RSRVD2 12
389#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
390#define BF_CLKCTRL_EMI_RSRVD2(v) \
391 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
392#define BP_CLKCTRL_EMI_DIV_XTAL 8 278#define BP_CLKCTRL_EMI_DIV_XTAL 8
393#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 279#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
394#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ 280#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
395 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) 281 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
396#define BP_CLKCTRL_EMI_RSRVD1 6
397#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
398#define BF_CLKCTRL_EMI_RSRVD1(v) \
399 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
400#define BP_CLKCTRL_EMI_DIV_EMI 0 282#define BP_CLKCTRL_EMI_DIV_EMI 0
401#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F 283#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
402#define BF_CLKCTRL_EMI_DIV_EMI(v) \ 284#define BF_CLKCTRL_EMI_DIV_EMI(v) \
@@ -406,12 +288,7 @@
406 288
407#define BP_CLKCTRL_SAIF0_CLKGATE 31 289#define BP_CLKCTRL_SAIF0_CLKGATE 31
408#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 290#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
409#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
410#define BM_CLKCTRL_SAIF0_BUSY 0x20000000 291#define BM_CLKCTRL_SAIF0_BUSY 0x20000000
411#define BP_CLKCTRL_SAIF0_RSRVD1 17
412#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
413#define BF_CLKCTRL_SAIF0_RSRVD1(v) \
414 (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
415#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 292#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
416#define BP_CLKCTRL_SAIF0_DIV 0 293#define BP_CLKCTRL_SAIF0_DIV 0
417#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF 294#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
@@ -422,12 +299,7 @@
422 299
423#define BP_CLKCTRL_SAIF1_CLKGATE 31 300#define BP_CLKCTRL_SAIF1_CLKGATE 31
424#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 301#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
425#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
426#define BM_CLKCTRL_SAIF1_BUSY 0x20000000 302#define BM_CLKCTRL_SAIF1_BUSY 0x20000000
427#define BP_CLKCTRL_SAIF1_RSRVD1 17
428#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
429#define BF_CLKCTRL_SAIF1_RSRVD1(v) \
430 (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
431#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 303#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
432#define BP_CLKCTRL_SAIF1_DIV 0 304#define BP_CLKCTRL_SAIF1_DIV 0
433#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF 305#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
@@ -438,12 +310,7 @@
438 310
439#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31 311#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31
440#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 312#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
441#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000
442#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 313#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
443#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14
444#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000
445#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \
446 (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
447#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 314#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
448#define BP_CLKCTRL_DIS_LCDIF_DIV 0 315#define BP_CLKCTRL_DIS_LCDIF_DIV 0
449#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF 316#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
@@ -453,12 +320,7 @@
453#define HW_CLKCTRL_ETM (0x00000130) 320#define HW_CLKCTRL_ETM (0x00000130)
454 321
455#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 322#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
456#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
457#define BM_CLKCTRL_ETM_BUSY 0x20000000 323#define BM_CLKCTRL_ETM_BUSY 0x20000000
458#define BP_CLKCTRL_ETM_RSRVD1 8
459#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00
460#define BF_CLKCTRL_ETM_RSRVD1(v) \
461 (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
462#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 324#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
463#define BP_CLKCTRL_ETM_DIV 0 325#define BP_CLKCTRL_ETM_DIV 0
464#define BM_CLKCTRL_ETM_DIV 0x0000007F 326#define BM_CLKCTRL_ETM_DIV 0x0000007F
@@ -471,7 +333,6 @@
471#define BP_CLKCTRL_ENET_DISABLE 30 333#define BP_CLKCTRL_ENET_DISABLE 30
472#define BM_CLKCTRL_ENET_DISABLE 0x40000000 334#define BM_CLKCTRL_ENET_DISABLE 0x40000000
473#define BM_CLKCTRL_ENET_STATUS 0x20000000 335#define BM_CLKCTRL_ENET_STATUS 0x20000000
474#define BM_CLKCTRL_ENET_RSRVD1 0x10000000
475#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 336#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
476#define BP_CLKCTRL_ENET_DIV_TIME 21 337#define BP_CLKCTRL_ENET_DIV_TIME 21
477#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 338#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
@@ -493,37 +354,23 @@
493#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 354#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
494#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 355#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
495#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 356#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
496#define BP_CLKCTRL_ENET_RSRVD0 0
497#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF
498#define BF_CLKCTRL_ENET_RSRVD0(v) \
499 (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
500 357
501#define HW_CLKCTRL_HSADC (0x00000150) 358#define HW_CLKCTRL_HSADC (0x00000150)
502 359
503#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
504#define BM_CLKCTRL_HSADC_RESETB 0x40000000 360#define BM_CLKCTRL_HSADC_RESETB 0x40000000
505#define BP_CLKCTRL_HSADC_FREQDIV 28 361#define BP_CLKCTRL_HSADC_FREQDIV 28
506#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 362#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
507#define BF_CLKCTRL_HSADC_FREQDIV(v) \ 363#define BF_CLKCTRL_HSADC_FREQDIV(v) \
508 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) 364 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
509#define BP_CLKCTRL_HSADC_RSRVD1 0
510#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
511#define BF_CLKCTRL_HSADC_RSRVD1(v) \
512 (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
513 365
514#define HW_CLKCTRL_FLEXCAN (0x00000160) 366#define HW_CLKCTRL_FLEXCAN (0x00000160)
515 367
516#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000
517#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30 368#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30
518#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 369#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
519#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 370#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
520#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28 371#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28
521#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 372#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
522#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 373#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
523#define BP_CLKCTRL_FLEXCAN_RSRVD1 0
524#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF
525#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \
526 (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
527 374
528#define HW_CLKCTRL_FRAC0 (0x000001b0) 375#define HW_CLKCTRL_FRAC0 (0x000001b0)
529#define HW_CLKCTRL_FRAC0_SET (0x000001b4) 376#define HW_CLKCTRL_FRAC0_SET (0x000001b4)
@@ -564,10 +411,6 @@
564#define HW_CLKCTRL_FRAC1_CLR (0x000001c8) 411#define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
565#define HW_CLKCTRL_FRAC1_TOG (0x000001cc) 412#define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
566 413
567#define BP_CLKCTRL_FRAC1_RSRVD2 24
568#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
569#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
570 (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
571#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23 414#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23
572#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 415#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
573#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 416#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
@@ -595,22 +438,10 @@
595#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) 438#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
596#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) 439#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
597 440
598#define BP_CLKCTRL_CLKSEQ_RSRVD0 19
599#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000
600#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
601 (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
602#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 441#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
603#define BP_CLKCTRL_CLKSEQ_RSRVD1 15
604#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000
605#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
606 (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
607#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 442#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
608#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 443#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
609#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 444#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
610#define BP_CLKCTRL_CLKSEQ_RSRVD2 9
611#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00
612#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \
613 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
614#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 445#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
615#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 446#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
616#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 447#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
@@ -623,10 +454,6 @@
623 454
624#define HW_CLKCTRL_RESET (0x000001e0) 455#define HW_CLKCTRL_RESET (0x000001e0)
625 456
626#define BP_CLKCTRL_RESET_RSRVD 6
627#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0
628#define BF_CLKCTRL_RESET_RSRVD(v) \
629 (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
630#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 457#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
631#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 458#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
632#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 459#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
@@ -640,10 +467,6 @@
640#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 467#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
641#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ 468#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
642 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) 469 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
643#define BP_CLKCTRL_STATUS_RSRVD 0
644#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
645#define BF_CLKCTRL_STATUS_RSRVD(v) \
646 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
647 470
648#define HW_CLKCTRL_VERSION (0x00000200) 471#define HW_CLKCTRL_VERSION (0x00000200)
649 472
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 9343d7edd4f6..20ec3bddf7cd 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -22,6 +22,7 @@
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/module.h>
25 26
26#include <asm/proc-fns.h> 27#include <asm/proc-fns.h>
27#include <asm/system.h> 28#include <asm/system.h>
@@ -135,3 +136,4 @@ error:
135 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); 136 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
136 return -ETIMEDOUT; 137 return -ETIMEDOUT;
137} 138}
139EXPORT_SYMBOL(mxs_reset_block);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 02:11:10 -0500