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authorShawn Guo <shawn.guo@linaro.org>2013-03-29 01:53:11 -0400
committerShawn Guo <shawn.guo@linaro.org>2013-04-01 08:42:23 -0400
commit0b48d3a6fbac641d1da12bbe202ec82ff0c89148 (patch)
treec35489ed45797c3d3aa49c9b59d6cb4df47e0cbc /arch/arm/mach-mxs
parent39490ab0ff49138c8613d95ea13b79c8159f306f (diff)
ARM: mxs: remove unused headers
Most of the stuff in the headers are used nowhere now. Move a few things that are useful for mach-mxs.c into there and remove the headers. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-mxs')
-rw-r--r--arch/arm/mach-mxs/include/mach/digctl.h22
-rw-r--r--arch/arm/mach-mxs/include/mach/mx23.h169
-rw-r--r--arch/arm/mach-mxs/include/mach/mx28.h225
-rw-r--r--arch/arm/mach-mxs/include/mach/mxs.h115
-rw-r--r--arch/arm/mach-mxs/mach-mxs.c29
5 files changed, 27 insertions, 533 deletions
diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h
deleted file mode 100644
index 17964066303f..000000000000
--- a/arch/arm/mach-mxs/include/mach/digctl.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __MACH_DIGCTL_H__
10#define __MACH_DIGCTL_H__
11
12/* MXS DIGCTL SAIF CLKMUX */
13#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0
14#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1
15#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2
16#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3
17
18#define HW_DIGCTL_CTRL 0x0
19#define BP_DIGCTL_CTRL_SAIF_CLKMUX 10
20#define BM_DIGCTL_CTRL_SAIF_CLKMUX (0x3 << 10)
21#define HW_DIGCTL_CHIPID 0x310
22#endif
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
deleted file mode 100644
index 599094bc99de..000000000000
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ /dev/null
@@ -1,169 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_MX23_H__
20#define __MACH_MX23_H__
21
22#include <mach/mxs.h>
23
24/*
25 * OCRAM
26 */
27#define MX23_OCRAM_BASE_ADDR 0x00000000
28#define MX23_OCRAM_SIZE SZ_32K
29
30/*
31 * IO
32 */
33#define MX23_IO_BASE_ADDR 0x80000000
34#define MX23_IO_SIZE SZ_1M
35
36#define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x000000)
37#define MX23_APBH_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x004000)
38#define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000)
39#define MX23_GPMI_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00c000)
40#define MX23_SSP1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x010000)
41#define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000)
42#define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000)
43#define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x020000)
44#define MX23_APBX_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x024000)
45#define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000)
46#define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000)
47#define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000)
48#define MX23_AXI_AHB0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02e000)
49#define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x030000)
50#define MX23_SSP2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x034000)
51#define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000)
52#define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x040000)
53#define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000)
54#define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000)
55#define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000)
56#define MX23_AUDIOOUT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x048000)
57#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000)
58#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000)
59#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000)
60#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
61#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000)
62#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000)
63#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000)
64#define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000)
65#define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000)
66#define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x070000)
67#define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000)
68#define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x080000)
69#define MX23_DRAM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x0e0000)
70
71#define MX23_IO_P2V(x) MXS_IO_P2V(x)
72#define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x))
73
74/*
75 * IRQ
76 */
77#define MX23_INT_DUART 0
78#define MX23_INT_COMMS_RX 1
79#define MX23_INT_COMMS_TX 1
80#define MX23_INT_SSP2_ERROR 2
81#define MX23_INT_VDD5V 3
82#define MX23_INT_HEADPHONE_SHORT 4
83#define MX23_INT_DAC_DMA 5
84#define MX23_INT_DAC_ERROR 6
85#define MX23_INT_ADC_DMA 7
86#define MX23_INT_ADC_ERROR 8
87#define MX23_INT_SPDIF_DMA 9
88#define MX23_INT_SAIF2_DMA 9
89#define MX23_INT_SPDIF_ERROR 10
90#define MX23_INT_SAIF1_IRQ 10
91#define MX23_INT_SAIF2_IRQ 10
92#define MX23_INT_USB_CTRL 11
93#define MX23_INT_USB_WAKEUP 12
94#define MX23_INT_GPMI_DMA 13
95#define MX23_INT_SSP1_DMA 14
96#define MX23_INT_SSP1_ERROR 15
97#define MX23_INT_GPIO0 16
98#define MX23_INT_GPIO1 17
99#define MX23_INT_GPIO2 18
100#define MX23_INT_SAIF1_DMA 19
101#define MX23_INT_SSP2_DMA 20
102#define MX23_INT_ECC8_IRQ 21
103#define MX23_INT_RTC_ALARM 22
104#define MX23_INT_AUART1_TX_DMA 23
105#define MX23_INT_AUART1 24
106#define MX23_INT_AUART1_RX_DMA 25
107#define MX23_INT_I2C_DMA 26
108#define MX23_INT_I2C_ERROR 27
109#define MX23_INT_TIMER0 28
110#define MX23_INT_TIMER1 29
111#define MX23_INT_TIMER2 30
112#define MX23_INT_TIMER3 31
113#define MX23_INT_BATT_BRNOUT 32
114#define MX23_INT_VDDD_BRNOUT 33
115#define MX23_INT_VDDIO_BRNOUT 34
116#define MX23_INT_VDD18_BRNOUT 35
117#define MX23_INT_TOUCH_DETECT 36
118#define MX23_INT_LRADC_CH0 37
119#define MX23_INT_LRADC_CH1 38
120#define MX23_INT_LRADC_CH2 39
121#define MX23_INT_LRADC_CH3 40
122#define MX23_INT_LRADC_CH4 41
123#define MX23_INT_LRADC_CH5 42
124#define MX23_INT_LRADC_CH6 43
125#define MX23_INT_LRADC_CH7 44
126#define MX23_INT_LCDIF_DMA 45
127#define MX23_INT_LCDIF_ERROR 46
128#define MX23_INT_DIGCTL_DEBUG_TRAP 47
129#define MX23_INT_RTC_1MSEC 48
130#define MX23_INT_DRI_DMA 49
131#define MX23_INT_DRI_ATTENTION 50
132#define MX23_INT_GPMI_ATTENTION 51
133#define MX23_INT_IR 52
134#define MX23_INT_DCP_VMI 53
135#define MX23_INT_DCP 54
136#define MX23_INT_BCH 56
137#define MX23_INT_PXP 57
138#define MX23_INT_AUART2_TX_DMA 58
139#define MX23_INT_AUART2 59
140#define MX23_INT_AUART2_RX_DMA 60
141#define MX23_INT_VDAC_DETECT 61
142#define MX23_INT_VDD5V_DROOP 64
143#define MX23_INT_DCDC4P2_BO 65
144
145/*
146 * APBH DMA
147 */
148#define MX23_DMA_SSP1 1
149#define MX23_DMA_SSP2 2
150#define MX23_DMA_GPMI0 4
151#define MX23_DMA_GPMI1 5
152#define MX23_DMA_GPMI2 6
153#define MX23_DMA_GPMI3 7
154
155/*
156 * APBX DMA
157 */
158#define MX23_DMA_ADC 0
159#define MX23_DMA_DAC 1
160#define MX23_DMA_SPDIF 2
161#define MX23_DMA_I2C 3
162#define MX23_DMA_SAIF0 4
163#define MX23_DMA_UART0_RX 6
164#define MX23_DMA_UART0_TX 7
165#define MX23_DMA_UART1_RX 8
166#define MX23_DMA_UART1_TX 9
167#define MX23_DMA_SAIF1 10
168
169#endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
deleted file mode 100644
index 30c7990f3c01..000000000000
--- a/arch/arm/mach-mxs/include/mach/mx28.h
+++ /dev/null
@@ -1,225 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_MX28_H__
20#define __MACH_MX28_H__
21
22#include <mach/mxs.h>
23
24/*
25 * OCRAM
26 */
27#define MX28_OCRAM_BASE_ADDR 0x00000000
28#define MX28_OCRAM_SIZE SZ_128K
29
30/*
31 * IO
32 */
33#define MX28_IO_BASE_ADDR 0x80000000
34#define MX28_IO_SIZE SZ_1M
35
36#define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000)
37#define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000)
38#define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000)
39#define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000)
40#define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000)
41#define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000)
42#define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000)
43#define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000)
44#define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000)
45#define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000)
46#define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000)
47#define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000)
48#define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000)
49#define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000)
50#define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000)
51#define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000)
52#define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000)
53#define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000)
54#define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000)
55#define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000)
56#define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000)
57#define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000)
58#define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200)
59#define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300)
60#define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400)
61#define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500)
62#define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700)
63#define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800)
64#define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000)
65#define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000)
66#define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000)
67#define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000)
68#define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000)
69#define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000)
70#define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000)
71#define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000)
72#define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000)
73#define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000)
74#define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000)
75#define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000)
76#define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000)
77#define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000)
78#define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000)
79#define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000)
80#define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000)
81#define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000)
82#define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000)
83#define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000)
84#define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000)
85#define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000)
86#define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000)
87#define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000)
88#define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000)
89
90#define MX28_IO_P2V(x) MXS_IO_P2V(x)
91#define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x))
92
93/*
94 * IRQ
95 */
96#define MX28_INT_BATT_BRNOUT 0
97#define MX28_INT_VDDD_BRNOUT 1
98#define MX28_INT_VDDIO_BRNOUT 2
99#define MX28_INT_VDDA_BRNOUT 3
100#define MX28_INT_VDD5V_DROOP 4
101#define MX28_INT_DCDC4P2_BRNOUT 5
102#define MX28_INT_VDD5V 6
103#define MX28_INT_CAN0 8
104#define MX28_INT_CAN1 9
105#define MX28_INT_LRADC_TOUCH 10
106#define MX28_INT_HSADC 13
107#define MX28_INT_LRADC_THRESH0 14
108#define MX28_INT_LRADC_THRESH1 15
109#define MX28_INT_LRADC_CH0 16
110#define MX28_INT_LRADC_CH1 17
111#define MX28_INT_LRADC_CH2 18
112#define MX28_INT_LRADC_CH3 19
113#define MX28_INT_LRADC_CH4 20
114#define MX28_INT_LRADC_CH5 21
115#define MX28_INT_LRADC_CH6 22
116#define MX28_INT_LRADC_CH7 23
117#define MX28_INT_LRADC_BUTTON0 24
118#define MX28_INT_LRADC_BUTTON1 25
119#define MX28_INT_PERFMON 27
120#define MX28_INT_RTC_1MSEC 28
121#define MX28_INT_RTC_ALARM 29
122#define MX28_INT_COMMS 31
123#define MX28_INT_EMI_ERR 32
124#define MX28_INT_LCDIF 38
125#define MX28_INT_PXP 39
126#define MX28_INT_BCH 41
127#define MX28_INT_GPMI 42
128#define MX28_INT_SPDIF_ERROR 45
129#define MX28_INT_DUART 47
130#define MX28_INT_TIMER0 48
131#define MX28_INT_TIMER1 49
132#define MX28_INT_TIMER2 50
133#define MX28_INT_TIMER3 51
134#define MX28_INT_DCP_VMI 52
135#define MX28_INT_DCP 53
136#define MX28_INT_DCP_SECURE 54
137#define MX28_INT_SAIF1 58
138#define MX28_INT_SAIF0 59
139#define MX28_INT_SPDIF_DMA 66
140#define MX28_INT_I2C0_DMA 68
141#define MX28_INT_I2C1_DMA 69
142#define MX28_INT_AUART0_RX_DMA 70
143#define MX28_INT_AUART0_TX_DMA 71
144#define MX28_INT_AUART1_RX_DMA 72
145#define MX28_INT_AUART1_TX_DMA 73
146#define MX28_INT_AUART2_RX_DMA 74
147#define MX28_INT_AUART2_TX_DMA 75
148#define MX28_INT_AUART3_RX_DMA 76
149#define MX28_INT_AUART3_TX_DMA 77
150#define MX28_INT_AUART4_RX_DMA 78
151#define MX28_INT_AUART4_TX_DMA 79
152#define MX28_INT_SAIF0_DMA 80
153#define MX28_INT_SAIF1_DMA 81
154#define MX28_INT_SSP0_DMA 82
155#define MX28_INT_SSP1_DMA 83
156#define MX28_INT_SSP2_DMA 84
157#define MX28_INT_SSP3_DMA 85
158#define MX28_INT_LCDIF_DMA 86
159#define MX28_INT_HSADC_DMA 87
160#define MX28_INT_GPMI_DMA 88
161#define MX28_INT_DIGCTL_DEBUG_TRAP 89
162#define MX28_INT_USB1 92
163#define MX28_INT_USB0 93
164#define MX28_INT_USB1_WAKEUP 94
165#define MX28_INT_USB0_WAKEUP 95
166#define MX28_INT_SSP0_ERROR 96
167#define MX28_INT_SSP1_ERROR 97
168#define MX28_INT_SSP2_ERROR 98
169#define MX28_INT_SSP3_ERROR 99
170#define MX28_INT_ENET_SWI 100
171#define MX28_INT_ENET_MAC0 101
172#define MX28_INT_ENET_MAC1 102
173#define MX28_INT_ENET_MAC0_1588 103
174#define MX28_INT_ENET_MAC1_1588 104
175#define MX28_INT_I2C1_ERROR 110
176#define MX28_INT_I2C0_ERROR 111
177#define MX28_INT_AUART0 112
178#define MX28_INT_AUART1 113
179#define MX28_INT_AUART2 114
180#define MX28_INT_AUART3 115
181#define MX28_INT_AUART4 116
182#define MX28_INT_GPIO4 123
183#define MX28_INT_GPIO3 124
184#define MX28_INT_GPIO2 125
185#define MX28_INT_GPIO1 126
186#define MX28_INT_GPIO0 127
187
188/*
189 * APBH DMA
190 */
191#define MX28_DMA_SSP0 0
192#define MX28_DMA_SSP1 1
193#define MX28_DMA_SSP2 2
194#define MX28_DMA_SSP3 3
195#define MX28_DMA_GPMI0 4
196#define MX28_DMA_GPMI1 5
197#define MX28_DMA_GPMI2 6
198#define MX28_DMA_GPMI3 7
199#define MX28_DMA_GPMI4 8
200#define MX28_DMA_GPMI5 9
201#define MX28_DMA_GPMI6 10
202#define MX28_DMA_GPMI7 11
203#define MX28_DMA_HSADC 12
204#define MX28_DMA_LCDIF 13
205
206/*
207 * APBX DMA
208 */
209#define MX28_DMA_AUART4_RX 0
210#define MX28_DMA_AUART4_TX 1
211#define MX28_DMA_SPDIF_TX 2
212#define MX28_DMA_SAIF0 4
213#define MX28_DMA_SAIF1 5
214#define MX28_DMA_I2C0 6
215#define MX28_DMA_I2C1 7
216#define MX28_DMA_AUART0_RX 8
217#define MX28_DMA_AUART0_TX 9
218#define MX28_DMA_AUART1_RX 10
219#define MX28_DMA_AUART1_TX 11
220#define MX28_DMA_AUART2_RX 12
221#define MX28_DMA_AUART2_TX 13
222#define MX28_DMA_AUART3_RX 14
223#define MX28_DMA_AUART3_TX 15
224
225#endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
deleted file mode 100644
index 5820b047ea2e..000000000000
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_MXS_H__
20#define __MACH_MXS_H__
21
22#ifndef __ASSEMBLER__
23#include <linux/io.h>
24#endif
25#include <mach/digctl.h>
26
27/*
28 * IO addresses common to MXS-based
29 */
30#define MXS_IO_BASE_ADDR 0x80000000
31#define MXS_IO_SIZE SZ_1M
32
33#define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000)
34#define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000)
35#define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000)
36#define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000)
37#define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000)
38#define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000)
39#define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000)
40#define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000)
41#define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000)
42#define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000)
43#define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000)
44#define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000)
45#define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000)
46#define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000)
47#define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000)
48#define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000)
49#define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000)
50#define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000)
51#define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000)
52#define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000)
53#define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000)
54#define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000)
55#define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000)
56#define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000)
57
58/*
59 * It maps the whole address space to [0xf4000000, 0xf50fffff].
60 *
61 * OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000
62 * IO 0x80000000+0x100000 -> 0xf5000000+0x100000
63 */
64#define MXS_IO_P2V(x) (0xf4000000 + \
65 (((x) & 0x80000000) >> 7) + \
66 (((x) & 0x000fffff)))
67
68#define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x))
69
70#define mxs_map_entry(soc, name, _type) { \
71 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
72 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
73 .length = soc ## _ ## name ## _SIZE, \
74 .type = _type, \
75}
76
77#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
78
79#define MXS_SET_ADDR 0x4
80#define MXS_CLR_ADDR 0x8
81#define MXS_TOG_ADDR 0xc
82
83#ifndef __ASSEMBLER__
84static inline void __mxs_setl(u32 mask, void __iomem *reg)
85{
86 __raw_writel(mask, reg + MXS_SET_ADDR);
87}
88
89static inline void __mxs_clrl(u32 mask, void __iomem *reg)
90{
91 __raw_writel(mask, reg + MXS_CLR_ADDR);
92}
93
94static inline void __mxs_togl(u32 mask, void __iomem *reg)
95{
96 __raw_writel(mask, reg + MXS_TOG_ADDR);
97}
98
99/*
100 * MXS CPU types
101 */
102#define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID)
103
104static inline int cpu_is_mx23(void)
105{
106 return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780);
107}
108
109static inline int cpu_is_mx28(void)
110{
111 return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800);
112}
113#endif
114
115#endif /* __MACH_MXS_H__ */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index a6e1ccb05066..16870bf853b8 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -31,8 +31,33 @@
31#include <asm/mach/map.h> 31#include <asm/mach/map.h>
32#include <asm/mach/time.h> 32#include <asm/mach/time.h>
33#include <asm/system_misc.h> 33#include <asm/system_misc.h>
34#include <mach/digctl.h> 34
35#include <mach/mxs.h> 35/* MXS DIGCTL SAIF CLKMUX */
36#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0
37#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1
38#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2
39#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3
40
41#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
42
43#define MXS_SET_ADDR 0x4
44#define MXS_CLR_ADDR 0x8
45#define MXS_TOG_ADDR 0xc
46
47static inline void __mxs_setl(u32 mask, void __iomem *reg)
48{
49 __raw_writel(mask, reg + MXS_SET_ADDR);
50}
51
52static inline void __mxs_clrl(u32 mask, void __iomem *reg)
53{
54 __raw_writel(mask, reg + MXS_CLR_ADDR);
55}
56
57static inline void __mxs_togl(u32 mask, void __iomem *reg)
58{
59 __raw_writel(mask, reg + MXS_TOG_ADDR);
60}
36 61
37static struct fb_videomode mx23evk_video_modes[] = { 62static struct fb_videomode mx23evk_video_modes[] = {
38 { 63 {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 20:33:39 -0500