Merge branch 'next/board' of git://git.linaro.org/people/arnd/arm-soc

* 'next/board' of git://git.linaro.org/people/arnd/arm-soc: (34 commits)
  ep93xx: add support Vision EP9307 SoM
  ARM: mxs: Add initial support for DENX MX28
  ARM: EXYNOS4: Add support SMDK4412 Board
  ARM: EXYNOS4: Add MCT support for EXYNOS4412
  ARM: EXYNOS4: Add functions for gic interrupt handling
  ARM: EXYNOS4: Add support clock for EXYNOS4412
  ARM: EXYNOS4: Add support new EXYNOS4412 SoC
  ARM: EXYNOS4: Add support MCT PPI for EXYNOS4212
  ARM: EXYNOS4: Add support PPI in external GIC
  ARM: EXYNOS4: convert boot_params to atag_offset
  ixp4xx: support omicron ixp425 based boards
  ARM: EXYNOS4: Add support SMDK4212 Board
  ARM: EXYNOS4: Add support PM for EXYNOS4212
  ARM: EXYNOS4: Add support clock for EXYNOS4212
  ARM: EXYNOS4: Add support new EXYNOS4212 SoC
  at91: USB-A9G20 C01 & C11 board support
  at91: merge board USB-A9260 and USB-A9263 together
  at91: add support for RSIs EWS board
  ARM: SAMSUNG: Fix mask value for S5P64X0 CPU IDs
  ARM: SAMSUNG: Fix mask for S3C64xx CPU IDs
  ...

1 files changed, 11 insertions, 5 deletions

diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index ba532279d1a1..7fa1ac4de7d8 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -738,11 +738,17 @@ static int clk_misc_init(void)
         __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
 
-        /* Extra fec clock setting */
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
-        reg &= ~BM_CLKCTRL_ENET_SLEEP;
-        reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+        /*
+         * Extra fec clock setting
+         * The DENX M28 uses an external clock source
+         * and the clock output must not be enabled
+         */
+        if (!machine_is_m28evk()) {
+                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+                reg &= ~BM_CLKCTRL_ENET_SLEEP;
+                reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
+                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+        }
 
         /*
          * 480 MHz seems too high to be ssp clock source directly,