ARM: mxs: Add initial support for DENX MX28

Added initial support for DENX M28 module and M28EVK
board. Ethernet(FEC), SDHC, Display are supported.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 11 insertions, 5 deletions

diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5dcc59d5b9ec..31223106ad6a 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -738,11 +738,17 @@ static int clk_misc_init(void)
         __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
 
-        /* Extra fec clock setting */
-        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
-        reg &= ~BM_CLKCTRL_ENET_SLEEP;
-        reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+        /*
+         * Extra fec clock setting
+         * The DENX M28 uses an external clock source
+         * and the clock output must not be enabled
+         */
+        if (!machine_is_m28evk()) {
+                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+                reg &= ~BM_CLKCTRL_ENET_SLEEP;
+                reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
+                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+        }
 
         /*
          * 480 MHz seems too high to be ssp clock source directly,