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authorArnd Bergmann <arnd@arndb.de>2011-10-20 09:14:25 -0400
committerArnd Bergmann <arnd@arndb.de>2011-10-20 09:14:25 -0400
commitb4cbb8a4e602ea77b0525d06eff89c6a6070dab3 (patch)
treea5dd723679582505ef3905c90f0c2c032d191b94 /arch/arm/mach-mxs/clock-mx28.c
parent526b264163068f77c5f2409031f5e25caf3900a9 (diff)
parentc5d7a9230e5e277f262b6806b7f4d6b35de5a3fb (diff)
Merge branch 'imx-features-for-arnd' of git://git.pengutronix.de/git/imx/linux-2.6 into imx/devel
Conflicts: arch/arm/mach-mx5/clock-mx51-mx53.c arch/arm/mach-mx5/devices-imx53.h
Diffstat (limited to 'arch/arm/mach-mxs/clock-mx28.c')
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 7954013bd32f..e2fb70c6a745 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -740,11 +740,17 @@ static int clk_misc_init(void)
740 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, 740 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
741 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); 741 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
742 742
743 /* Extra fec clock setting */ 743 /*
744 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); 744 * Extra fec clock setting
745 reg &= ~BM_CLKCTRL_ENET_SLEEP; 745 * The DENX M28 uses an external clock source
746 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; 746 * and the clock output must not be enabled
747 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); 747 */
748 if (!machine_is_m28evk()) {
749 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
750 reg &= ~BM_CLKCTRL_ENET_SLEEP;
751 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
752 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
753 }
748 754
749 /* 755 /*
750 * 480 MHz seems too high to be ssp clock source directly, 756 * 480 MHz seems too high to be ssp clock source directly,