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authorShawn Guo <shawn.guo@freescale.com>2011-03-16 06:31:06 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2011-03-25 03:36:55 -0400
commit47babe692e90e0333b2448969639b8f0940e3682 (patch)
tree49357fe0074a4cf2a03bed616c891fe3aec69e9f /arch/arm/mach-mxs/clock-mx23.c
parent251290a6078cb88382344b3ee535ae8c6254c1b5 (diff)
ARM: mxs: dynamically allocate mmc device
Signed-off-by: Shawn Guo <shawn.guo@freescale.com> [ukleinek: fix naming to include complete device name in functions] Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mxs/clock-mx23.c')
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index d133c7f30940..c3577ea789ac 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -521,6 +521,15 @@ static int clk_misc_init(void)
521 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, 521 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
522 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); 522 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
523 523
524 /*
525 * 480 MHz seems too high to be ssp clock source directly,
526 * so set frac to get a 288 MHz ref_io.
527 */
528 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
529 reg &= ~BM_CLKCTRL_FRAC_IOFRAC;
530 reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
531 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
532
524 return 0; 533 return 0;
525} 534}
526 535
@@ -528,6 +537,12 @@ int __init mx23_clocks_init(void)
528{ 537{
529 clk_misc_init(); 538 clk_misc_init();
530 539
540 /*
541 * source ssp clock from ref_io than ref_xtal,
542 * as ref_xtal only provides 24 MHz as maximum.
543 */
544 clk_set_parent(&ssp_clk, &ref_io_clk);
545
531 clk_enable(&cpu_clk); 546 clk_enable(&cpu_clk);
532 clk_enable(&hbus_clk); 547 clk_enable(&hbus_clk);
533 clk_enable(&xbus_clk); 548 clk_enable(&xbus_clk);