Merge branch 'master' into for-next

Fast-forwarded to current state of Linus' tree as there are patches to be
applied for files that didn't exist on the old branch.

11 files changed, 194 insertions, 13 deletions

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 83ee08847d4d..159340da9191 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -165,6 +165,7 @@ config MACH_MX53_LOCO
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select IMX_HAVE_PLATFORM_GPIO_KEYS
         help
           Include support for MX53 LOCO platform. This includes specific
           configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 4f63048be3ca..0b9338cec516 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Object file lists.
-obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o
+obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o
 obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
 
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index b2ecd194e76d..bea4e4135f9d 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -228,13 +228,12 @@ static inline void babbage_fec_reset(void)
         int ret;
 
         /* reset FEC PHY */
-        ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
+        ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
+                                        GPIOF_OUT_INIT_LOW, "fec-phy-reset");
         if (ret) {
                 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
                 return;
         }
-        gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
-        gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
         msleep(1);
         gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
 }
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 7b5735c5ea59..2af3f43f74db 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -34,7 +34,7 @@
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx53.h>
 
-#define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
+#define MX53_EVK_FEC_PHY_RST    IMX_GPIO_NR(7, 6)
 #define EVK_ECSPI1_CS0          IMX_GPIO_NR(2, 30)
 #define EVK_ECSPI1_CS1          IMX_GPIO_NR(3, 19)
 
@@ -82,15 +82,14 @@ static inline void mx53_evk_fec_reset(void)
         int ret;
 
         /* reset FEC PHY */
-        ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
+        ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
+                                                        "fec-phy-reset");
         if (ret) {
                 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
                 return;
         }
-        gpio_direction_output(SMD_FEC_PHY_RST, 0);
-        gpio_set_value(SMD_FEC_PHY_RST, 0);
         msleep(1);
-        gpio_set_value(SMD_FEC_PHY_RST, 1);
+        gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
 }
 
 static struct fec_platform_data mx53_evk_fec_pdata = {
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 0a18f8d23eb0..10a1bea10548 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -36,6 +36,9 @@
 #include "crm_regs.h"
 #include "devices-imx53.h"
 
+#define MX53_LOCO_POWER                 IMX_GPIO_NR(1, 8)
+#define MX53_LOCO_UI1                   IMX_GPIO_NR(2, 14)
+#define MX53_LOCO_UI2                   IMX_GPIO_NR(2, 15)
 #define LOCO_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
 
 static iomux_v3_cfg_t mx53_loco_pads[] = {
@@ -180,6 +183,27 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
         MX53_PAD_GPIO_8__GPIO1_8,
 };
 
+#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)    \
+{                                                               \
+        .gpio           = gpio_num,                             \
+        .type           = EV_KEY,                               \
+        .code           = ev_code,                              \
+        .active_low     = act_low,                              \
+        .desc           = "btn " descr,                         \
+        .wakeup         = wake,                                 \
+}
+
+static const struct gpio_keys_button loco_buttons[] __initconst = {
+        GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
+        GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
+        GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
+};
+
+static const struct gpio_keys_platform_data loco_button_data __initconst = {
+        .buttons        = loco_buttons,
+        .nbuttons       = ARRAY_SIZE(loco_buttons),
+};
+
 static inline void mx53_loco_fec_reset(void)
 {
         int ret;
@@ -215,6 +239,7 @@ static void __init mx53_loco_board_init(void)
         imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
         imx53_add_sdhci_esdhc_imx(0, NULL);
         imx53_add_sdhci_esdhc_imx(2, NULL);
+        imx_add_gpio_keys(&loco_button_data);
 }
 
 static void __init mx53_loco_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 652ace413825..fdbc05ed5513 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -865,6 +865,13 @@ static struct clk aips_tz2_clk = {
         .disable = _clk_ccgr_disable_inwait,
 };
 
+static struct clk gpc_dvfs_clk = {
+        .enable_reg = MXC_CCM_CCGR5,
+        .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+        .enable = _clk_ccgr_enable,
+        .disable = _clk_ccgr_disable,
+};
+
 static struct clk gpt_32k_clk = {
         .id = 0,
         .parent = &ckil_clk,
@@ -1448,6 +1455,7 @@ static struct clk_lookup mx51_lookups[] = {
         _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
         _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
         _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
+        _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
 };
 
 static struct clk_lookup mx53_lookups[] = {
@@ -1511,6 +1519,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
         clk_enable(&iim_clk);
         mx51_revision();
         clk_disable(&iim_clk);
+        mx51_display_revision();
 
         /* move usb_phy_clk to 24MHz */
         clk_set_parent(&usb_phy1_clk, &osc_clk);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index df46b5e60857..472bdfab2e55 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -21,6 +21,7 @@
 static int cpu_silicon_rev = -1;
 
 #define IIM_SREV 0x24
+#define MX50_HW_ADADIG_DIGPROG  0xB0
 
 static int get_mx51_srev(void)
 {
@@ -51,6 +52,26 @@ int mx51_revision(void)
 }
 EXPORT_SYMBOL(mx51_revision);
 
+void mx51_display_revision(void)
+{
+        int rev;
+        char *srev;
+        rev = mx51_revision();
+
+        switch (rev) {
+        case IMX_CHIP_REVISION_2_0:
+                srev = IMX_CHIP_REVISION_2_0_STRING;
+                break;
+        case IMX_CHIP_REVISION_3_0:
+                srev = IMX_CHIP_REVISION_3_0_STRING;
+                break;
+        default:
+                srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
+        }
+        printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
+}
+EXPORT_SYMBOL(mx51_display_revision);
+
 #ifdef CONFIG_NEON
 
 /*
@@ -107,6 +128,44 @@ int mx53_revision(void)
 }
 EXPORT_SYMBOL(mx53_revision);
 
+static int get_mx50_srev(void)
+{
+        void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
+        u32 rev;
+
+        if (!anatop) {
+                cpu_silicon_rev = -EINVAL;
+                return 0;
+        }
+
+        rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
+        rev &= 0xff;
+
+        iounmap(anatop);
+        if (rev == 0x0)
+                return IMX_CHIP_REVISION_1_0;
+        else if (rev == 0x1)
+                return IMX_CHIP_REVISION_1_1;
+        return 0;
+}
+
+/*
+ * Returns:
+ *      the silicon revision of the cpu
+ *      -EINVAL - not a mx50
+ */
+int mx50_revision(void)
+{
+        if (!cpu_is_mx50())
+                return -EINVAL;
+
+        if (cpu_silicon_rev == -1)
+                cpu_silicon_rev = get_mx50_srev();
+
+        return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx50_revision);
+
 static int __init post_cpu_init(void)
 {
         unsigned int reg;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index e83ffadb65f8..4a8550529b04 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -212,7 +212,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
 
         gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
         gpio_direction_input(MBIMX51_TSC2007_GPIO);
-        set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
+        irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
         i2c_register_board_info(1, mbimx51_i2c_devices,
                                 ARRAY_SIZE(mbimx51_i2c_devices));
 
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index c372a4373691..e6c1119c20ae 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -67,6 +67,10 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         MX51_PAD_SD1_DATA1__SD1_DATA1,
         MX51_PAD_SD1_DATA2__SD1_DATA2,
         MX51_PAD_SD1_DATA3__SD1_DATA3,
+        /* SD1 CD */
+        _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
+                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
 
 #define GPIO_LED1       IMX_GPIO_NR(3, 30)
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index 51a67fc7f0ef..d0c7075937cf 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -42,7 +42,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <asm/mach-types.h>
 
 #include "devices-imx51.h"
 #include "devices.h"
@@ -572,8 +571,10 @@ static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
 
 static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
         .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
-        .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
-        .regulators = mx51_efika_regulators,
+        .regulators = {
+                .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
+                .regulators = mx51_efika_regulators,
+        },
 };
 
 static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
new file mode 100644
index 000000000000..76ae8dc33e00
--- /dev/null
+++ b/arch/arm/mach-mx5/system.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include "crm_regs.h"
+
+/* set cpu low power mode before WFI instruction. This function is called
+  * mx5 because it can be used for mx50, mx51, and mx53.*/
+void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
+{
+        u32 plat_lpc, arm_srpgcr, ccm_clpcr;
+        u32 empgc0, empgc1;
+        int stop_mode = 0;
+
+        /* always allow platform to issue a deep sleep mode request */
+        plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
+            ~(MXC_CORTEXA8_PLAT_LPC_DSM);
+        ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
+        arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
+        empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
+        empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
+
+        switch (mode) {
+        case WAIT_CLOCKED:
+                break;
+        case WAIT_UNCLOCKED:
+                ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
+                break;
+        case WAIT_UNCLOCKED_POWER_OFF:
+        case STOP_POWER_OFF:
+                plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
+                            | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
+                if (mode == WAIT_UNCLOCKED_POWER_OFF) {
+                        ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
+                        ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
+                        ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
+                        stop_mode = 0;
+                } else {
+                        ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
+                        ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
+                        ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
+                        ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
+                        stop_mode = 1;
+                }
+                arm_srpgcr |= MXC_SRPGCR_PCR;
+
+                if (tzic_enable_wake(1) != 0)
+                        return;
+                break;
+        case STOP_POWER_ON:
+                ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
+                break;
+        default:
+                printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
+                return;
+        }
+
+        __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
+        __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
+        __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
+
+        /* Enable NEON SRPG for all but MX50TO1.0. */
+        if (mx50_revision() != IMX_CHIP_REVISION_1_0)
+                __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
+
+        if (stop_mode) {
+                empgc0 |= MXC_SRPGCR_PCR;
+                empgc1 |= MXC_SRPGCR_PCR;
+
+                __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
+                __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
+        }
+}