Merge branch 'for-rmk-next' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable

11 files changed, 480 insertions, 180 deletions

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 0848db5dd364..fad31cc5004b 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -5,11 +5,14 @@ config ARCH_MX51
         default y
         select MXC_TZIC
         select ARCH_MXC_IOMUX_V3
+        select ARCH_MXC_AUDMUX_V2
 
 comment "MX5 platforms:"
 
 config MACH_MX51_BABBAGE
         bool "Support MX51 BABBAGE platforms"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX51 Babbage platform, also known as MX51EVK in
           u-boot. This includes specific configurations for the board and its
@@ -17,6 +20,8 @@ config MACH_MX51_BABBAGE
 
 config MACH_MX51_3DS
         bool "Support MX51PDK (3DS)"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_DEBUG_BOARD
         help
           Include support for MX51PDK (3DS) platform. This includes specific
@@ -24,6 +29,8 @@ config MACH_MX51_3DS
 
 config MACH_EUKREA_CPUIMX51
         bool "Support Eukrea CPUIMX51 module"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for Eukrea CPUIMX51 platform. This includes
           specific configurations for the module and its peripherals.
@@ -42,4 +49,11 @@ config MACH_EUKREA_MBIMX51_BASEBOARD
 
 endchoice
 
+config MACH_MX51_EFIKAMX
+        bool "Support MX51 Genesi Efika MX nettop"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for Genesi Efika MX nettop. This includes specific
+          configurations for the board and its peripherals.
+
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 86c66e7f52f3..d1aac9c3d33c 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
+obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 623607a20f57..61f051043bbc 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -28,9 +28,7 @@
 #include <mach/eukrea-baseboards.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
 #include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
@@ -39,6 +37,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define CPUIMX51_USBH1_STP      (0*32 + 27)
@@ -109,7 +108,6 @@ static struct platform_device serial_device = {
 #endif
 
 static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
         &serial_device,
 #endif
@@ -148,11 +146,12 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
         MX51_PAD_USBH1_STP__USBH1_STP,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = {
+static const
+struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -239,7 +238,7 @@ static void __init eukrea_cpuimx51_init(void)
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
                                         ARRAY_SIZE(eukrea_cpuimx51_pads));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx51_add_imx_uart(0, &uart_pdata);
         gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
         gpio_direction_input(CPUIMX51_QUARTA_GPIO);
         gpio_free(CPUIMX51_QUARTA_GPIO);
@@ -253,9 +252,10 @@ static void __init eukrea_cpuimx51_init(void)
         gpio_direction_input(CPUIMX51_QUARTD_GPIO);
         gpio_free(CPUIMX51_QUARTD_GPIO);
 
+        imx51_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data);
+        imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
         i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
 
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index f95c2fd94667..ed08a2352a1a 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -13,6 +13,7 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -21,12 +22,13 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx51.h>
-#include <mach/imx-uart.h>
 #include <mach/3ds_debugboard.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define EXPIO_PARENT_INT        (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+#define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
 
 static struct pad_desc mx51_3ds_pads[] = {
         /* UART1 */
@@ -61,19 +63,25 @@ static struct pad_desc mx51_3ds_pads[] = {
         MX51_PAD_KEY_COL3__KEY_COL3,
         MX51_PAD_KEY_COL4__KEY_COL4,
         MX51_PAD_KEY_COL5__KEY_COL5,
+
+        /* eCSPI2 */
+        MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
+        MX51_PAD_NANDF_RB3__ECSPI2_MISO,
+        MX51_PAD_NANDF_D15__ECSPI2_MOSI,
+        MX51_PAD_NANDF_D12__GPIO_3_28,
 };
 
 /* Serial ports */
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static inline void mxc_init_imx_uart(void)
 {
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
@@ -127,6 +135,26 @@ static inline void mxc_init_keypad(void)
 }
 #endif
 
+static int mx51_3ds_spi2_cs[] = {
+        MXC_SPI_CS(0),
+        MX51_3DS_ECSPI2_CS,
+};
+
+static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
+        .chipselect     = mx51_3ds_spi2_cs,
+        .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
+};
+
+static struct spi_board_info mx51_3ds_spi_nor_device[] = {
+        {
+         .modalias = "m25p80",
+         .max_speed_hz = 25000000,      /* max spi clock (SCK) speed in HZ */
+         .bus_num = 1,
+         .chip_select = 1,
+         .mode = SPI_MODE_0,
+         .platform_data = NULL,},
+};
+
 /*
  * Board specific initialization.
  */
@@ -136,6 +164,10 @@ static void __init mxc_board_init(void)
                                         ARRAY_SIZE(mx51_3ds_pads));
         mxc_init_imx_uart();
 
+        imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
+        spi_register_board_info(mx51_3ds_spi_nor_device,
+                                ARRAY_SIZE(mx51_3ds_spi_nor_device));
+
         if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 printk(KERN_WARNING "Init of the debugboard failed, all "
                                     "devices on the board are unusable.\n");
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 6e384d92e625..23ee4a447406 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -17,12 +17,11 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/fsl_devices.h>
+#include <linux/fec.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
 #include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
@@ -31,11 +30,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define BABBAGE_USB_HUB_RESET   (0*32 + 7)      /* GPIO_1_7 */
 #define BABBAGE_USBH1_STP       (0*32 + 27)     /* GPIO_1_27 */
-#define BABBAGE_PHY_RESET (1*32 +5)     /* GPIO_2_5 */
+#define BABBAGE_PHY_RESET       (1*32 + 5)      /* GPIO_2_5 */
+#define BABBAGE_FEC_PHY_RESET   (1*32 + 14)     /* GPIO_2_14 */
 
 /* USB_CTRL_1 */
 #define MX51_USB_CTRL_1_OFFSET                  0x10
@@ -45,10 +46,6 @@
 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
 #define MX51_USB_PLL_DIV_24_MHZ 0x02
 
-static struct platform_device *devices[] __initdata = {
-        &mxc_fec_device,
-};
-
 static struct pad_desc mx51babbage_pads[] = {
         /* UART1 */
         MX51_PAD_UART1_RXD__UART1_RXD,
@@ -93,19 +90,41 @@ static struct pad_desc mx51babbage_pads[] = {
 
         /* USB HUB reset line*/
         MX51_PAD_GPIO_1_7__GPIO_1_7,
+
+        /* FEC */
+        MX51_PAD_EIM_EB2__FEC_MDIO,
+        MX51_PAD_EIM_EB3__FEC_RDAT1,
+        MX51_PAD_EIM_CS2__FEC_RDAT2,
+        MX51_PAD_EIM_CS3__FEC_RDAT3,
+        MX51_PAD_EIM_CS4__FEC_RX_ER,
+        MX51_PAD_EIM_CS5__FEC_CRS,
+        MX51_PAD_NANDF_RB2__FEC_COL,
+        MX51_PAD_NANDF_RB3__FEC_RXCLK,
+        MX51_PAD_NANDF_RB6__FEC_RDAT0,
+        MX51_PAD_NANDF_RB7__FEC_TDAT0,
+        MX51_PAD_NANDF_CS2__FEC_TX_ER,
+        MX51_PAD_NANDF_CS3__FEC_MDC,
+        MX51_PAD_NANDF_CS4__FEC_TDAT1,
+        MX51_PAD_NANDF_CS5__FEC_TDAT2,
+        MX51_PAD_NANDF_CS6__FEC_TDAT3,
+        MX51_PAD_NANDF_CS7__FEC_TX_EN,
+        MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+
+        /* FEC PHY reset line */
+        MX51_PAD_EIM_A20__GPIO_2_14,
 };
 
 /* Serial ports */
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static inline void mxc_init_imx_uart(void)
 {
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
@@ -113,7 +132,7 @@ static inline void mxc_init_imx_uart(void)
 }
 #endif /* SERIAL_IMX */
 
-static struct imxi2c_platform_data babbage_i2c_data = {
+static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -171,6 +190,22 @@ static inline void babbage_usbhub_reset(void)
         gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
 }
 
+static inline void babbage_fec_reset(void)
+{
+        int ret;
+
+        /* reset FEC PHY */
+        ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
+        if (ret) {
+                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+                return;
+        }
+        gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
+        gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
+        msleep(1);
+        gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
+}
+
 /* This function is board specific as the bit mask for the plldiv will also
 be different for other Freescale SoCs, thus a common bitmask is not
 possible and cannot get place in /plat-mxc/ehci.c.*/
@@ -178,7 +213,7 @@ static int initialize_otg_port(struct platform_device *pdev)
 {
         u32 v;
         void __iomem *usb_base;
-        u32 usbother_base;
+        void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -196,7 +231,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
 {
         u32 v;
         void __iomem *usb_base;
-        u32 usbother_base;
+        void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -250,10 +285,11 @@ static void __init mxc_board_init(void)
         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
                                         ARRAY_SIZE(mx51babbage_pads));
         mxc_init_imx_uart();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        babbage_fec_reset();
+        imx51_add_fec(NULL);
 
-        mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
-        mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
+        imx51_add_imx_i2c(0, &babbage_i2c_data);
+        imx51_add_imx_i2c(1, &babbage_i2c_data);
         mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
 
         if (otg_mode_host)
@@ -283,7 +319,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
         /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
         .phys_io = MX51_AIPS1_BASE_ADDR,
         .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
-        .boot_params = PHYS_OFFSET + 0x100,
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
         .init_irq = mx51_init_irq,
         .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
new file mode 100644
index 000000000000..b00502acdc15
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2010 Linaro Limited
+ *
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "devices.h"
+
+#define MX51_USB_PLL_DIV_24_MHZ 0x01
+
+static struct pad_desc mx51efikamx_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+};
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static const struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+/* This function is board specific as the bit mask for the plldiv will also
+ * be different for other Freescale SoCs, thus a common bitmask is not
+ * possible and cannot get place in /plat-mxc/ehci.c.
+ */
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_24_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init   = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+        .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
+static void __init mxc_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
+                                        ARRAY_SIZE(mx51efikamx_pads));
+        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        mxc_init_imx_uart();
+}
+
+static void __init mx51_efikamx_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+}
+
+static struct sys_timer mxc_timer = {
+        .init   = mx51_efikamx_timer_init,
+};
+
+MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
+        /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
+        .phys_io = MX51_AIPS1_BASE_ADDR,
+        .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_irq = mx51_init_irq,
+        .init_machine =  mxc_board_init,
+        .timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 57c10a9926cc..21cecc040172 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -41,34 +41,36 @@ static struct clk usboh3_clk;
 
 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
 
-static int _clk_ccgr_enable(struct clk *clk)
+static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
 {
-        u32 reg;
+        u32 reg = __raw_readl(clk->enable_reg);
+
+        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+        reg |= mode << clk->enable_shift;
 
-        reg = __raw_readl(clk->enable_reg);
-        reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
         __raw_writel(reg, clk->enable_reg);
+}
 
+static int _clk_ccgr_enable(struct clk *clk)
+{
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
         return 0;
 }
 
 static void _clk_ccgr_disable(struct clk *clk)
 {
-        u32 reg;
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
+}
 
+static int _clk_ccgr_enable_inrun(struct clk *clk)
+{
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
+        return 0;
 }
 
 static void _clk_ccgr_disable_inwait(struct clk *clk)
 {
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-        reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
+        _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
 }
 
 /*
@@ -571,6 +573,64 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
         return 0;
 }
 
+#define clk_nfc_set_parent      NULL
+
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+        unsigned long rate;
+        u32 reg, div;
+
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
+               MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
+        rate = clk_get_rate(clk->parent) / div;
+        WARN_ON(rate == 0);
+        return rate;
+}
+
+static unsigned long clk_nfc_round_rate(struct clk *clk,
+                                                unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+
+        if (!rate)
+                return -EINVAL;
+
+        div = parent_rate / rate;
+
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 8)
+                return -EINVAL;
+
+        return parent_rate / div;
+
+}
+
+static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, div;
+
+        div = clk_get_rate(clk->parent) / rate;
+        if (div == 0)
+                div++;
+        if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
+                return -EINVAL;
+
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+        reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+        __raw_writel(reg, MXC_CCM_CBCDR);
+
+        while (__raw_readl(MXC_CCM_CDHIPR) &
+                        MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
+        }
+
+        return 0;
+}
+
 static unsigned long clk_usboh3_get_rate(struct clk *clk)
 {
         u32 reg, prediv, podf;
@@ -620,6 +680,17 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
         return ckih2_reference;
 }
 
+static unsigned long clk_emi_slow_get_rate(struct clk *clk)
+{
+        u32 reg, div;
+
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
+               MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
+
+        return clk_get_rate(clk->parent) / div;
+}
+
 /* External high frequency clock */
 static struct clk ckih_clk = {
         .get_rate = get_high_reference_clock_rate,
@@ -762,45 +833,105 @@ static struct clk kpp_clk = {
         .id = 0,
 };
 
-#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)     \
+static struct clk emi_slow_clk = {
+        .parent = &pll2_sw_clk,
+        .enable_reg = MXC_CCM_CCGR5,
+        .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+        .enable = _clk_ccgr_enable,
+        .disable = _clk_ccgr_disable_inwait,
+        .get_rate = clk_emi_slow_get_rate,
+};
+
+#define DEFINE_CLOCK1(name, i, er, es, pfx, p, s)       \
         static struct clk name = {                      \
                 .id             = i,                    \
                 .enable_reg     = er,                   \
                 .enable_shift   = es,                   \
-                .get_rate       = gr,                   \
-                .set_rate       = sr,                   \
+                .get_rate       = pfx##_get_rate,       \
+                .set_rate       = pfx##_set_rate,       \
+                .round_rate     = pfx##_round_rate,     \
+                .set_parent     = pfx##_set_parent,     \
                 .enable         = _clk_ccgr_enable,     \
                 .disable        = _clk_ccgr_disable,    \
                 .parent         = p,                    \
                 .secondary      = s,                    \
         }
 
-/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
-   get_rate, set_rate, parent, secondary); */
+/* eCSPI */
+static unsigned long clk_ecspi_get_rate(struct clk *clk)
+{
+        u32 reg, pred, podf;
+
+        reg = __raw_readl(MXC_CCM_CSCDR2);
+
+        pred = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
+                        MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
+        podf = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
+                        MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
+
+        return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),
+                        (pred + 1) * (podf + 1));
+}
+
+static int clk_ecspi_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg, mux;
+
+        mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+                        &lp_apm_clk);
+
+        reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
+        reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
+static struct clk ecspi_main_clk = {
+        .parent = &pll3_sw_clk,
+        .get_rate = clk_ecspi_get_rate,
+        .set_parent = clk_ecspi_set_parent,
+};
+
+#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
+        static struct clk name = {                                      \
+                .id             = i,                                    \
+                .enable_reg     = er,                                   \
+                .enable_shift   = es,                                   \
+                .get_rate       = gr,                                   \
+                .set_rate       = sr,                                   \
+                .enable         = e,                                    \
+                .disable        = d,                                    \
+                .parent         = p,                                    \
+                .secondary      = s,                                    \
+        }
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                     \
+        DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
 
 /* Shared peripheral bus arbiter */
 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
 
 /* UART */
-DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
-        NULL,  NULL, &uart_root_clk, NULL);
-DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
-        NULL,  NULL, &uart_root_clk, NULL);
-DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
-        NULL,  NULL, &uart_root_clk, NULL);
 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
         NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
+DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
+DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
+        NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
 
 /* GPT */
-DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
-        NULL,  NULL, &ipg_clk, NULL);
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
+        NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
 
 /* I2C */
 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
@@ -814,6 +945,42 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
 
+/* NFC */
+DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
+        clk_nfc, &emi_slow_clk, NULL);
+
+/* SSI */
+DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
+        NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
+DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
+        NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
+
+/* eCSPI */
+DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+                NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+                &ipg_clk, &spba_clk);
+DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
+                NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
+DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
+                NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+                &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
+                NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
+
+/* CSPI */
+DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+                NULL, NULL, &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
+                NULL, NULL, &ipg_clk, &cspi_ipg_clk);
+
+/* SDMA */
+DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
+                NULL, NULL, &ahb_clk, NULL);
+
 #define _REGISTER_CLOCK(d, n, c) \
        { \
                 .dev_id = d, \
@@ -837,6 +1004,16 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
         _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
+        _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
+        _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
+        _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
+        _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
+        _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
+        _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
+        _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
new file mode 100644
index 000000000000..c233379256b8
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx51.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_fec_data imx51_fec_data __initconst;
+#define imx51_add_fec(pdata)    \
+        imx_add_fec(&imx51_fec_data, pdata)
+
+extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
+#define imx51_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
+
+extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst;
+#define imx51_add_imx_ssi(id, pdata)    \
+        imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst;
+#define imx51_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
+
+extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
+#define imx51_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
+
+extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
+#define imx51_add_cspi(pdata)   \
+        imx_add_spi_imx(&imx51_cspi_data, pdata)
+
+extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
+#define imx51_add_ecspi(id, pdata)      \
+        imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 1920ff4963b2..4c7be87a7c9d 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -17,120 +17,6 @@
 #include <mach/imx-uart.h>
 #include <mach/irqs.h>
 
-static struct resource uart0[] = {
-        {
-                .start = MX51_UART1_BASE_ADDR,
-                .end = MX51_UART1_BASE_ADDR + 0xfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_UART1,
-                .end = MX51_MXC_INT_UART1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = MX51_UART2_BASE_ADDR,
-                .end = MX51_UART2_BASE_ADDR + 0xfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_UART2,
-                .end = MX51_MXC_INT_UART2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = MX51_UART3_BASE_ADDR,
-                .end = MX51_UART3_BASE_ADDR + 0xfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_UART3,
-                .end = MX51_MXC_INT_UART3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource mxc_fec_resources[] = {
-        {
-                .start  = MX51_MXC_FEC_BASE_ADDR,
-                .end    = MX51_MXC_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX51_MXC_INT_FEC,
-                .end    = MX51_MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_fec_device = {
-        .name = "fec",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_fec_resources),
-        .resource = mxc_fec_resources,
-};
-
-static struct resource mxc_i2c0_resources[] = {
-        {
-                .start = MX51_I2C1_BASE_ADDR,
-                .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_I2C1,
-                .end = MX51_MXC_INT_I2C1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device0 = {
-        .name = "imx-i2c",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
-        .resource = mxc_i2c0_resources,
-};
-
-static struct resource mxc_i2c1_resources[] = {
-        {
-                .start = MX51_I2C2_BASE_ADDR,
-                .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX51_MXC_INT_I2C2,
-                .end = MX51_MXC_INT_I2C2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device1 = {
-        .name = "imx-i2c",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
-        .resource = mxc_i2c1_resources,
-};
-
 static struct resource mxc_hsi2c_resources[] = {
         {
                 .start = MX51_HSI2C_DMA_BASE_ADDR,
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index e509cfaad1d4..af1d07c0bbc1 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -1,12 +1,6 @@
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_hsi2c_device;
 extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index ffa93d1d6ef8..d0e417ce2c08 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -30,6 +30,7 @@
 
 #include <asm/mach/arch.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define MBIMX51_TSC2007_GPIO    (2*32 + 30)
@@ -114,7 +115,7 @@ static struct pad_desc mbimx51_pads[] = {
         MX51_PAD_KEY_COL3__KEY_COL3,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -172,8 +173,8 @@ void __init eukrea_mbimx51_baseboard_init(void)
         mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
                                         ARRAY_SIZE(mbimx51_pads));
 
-        mxc_register_device(&mxc_uart_device1, NULL);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx51_add_imx_uart(1, NULL);
+        imx51_add_imx_uart(2, &uart_pdata);
 
         gpio_request(MBIMX51_LED0, "LED0");
         gpio_direction_output(MBIMX51_LED0, 1);