aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-mx5/clock-mx51-mx53.c
diff options
context:
space:
mode:
authorArnaud Patard (Rtp) <arnaud.patard@rtp-net.org>2010-12-20 10:48:58 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2011-01-03 04:20:23 -0500
commit711669e5b80b6f2d88f61ed8a9681f83d8cbd201 (patch)
treebfb50f071e2d539e310aeb3767bfbce54267420f /arch/arm/mach-mx5/clock-mx51-mx53.c
parent8305ed75d1418f02933a48bcabdbb5032d885628 (diff)
mx51: fix usb clock support
Current code doesn't really enable the usb clocks so if they're disabled when booting linux, the kernel/machine will hang as soon as someone is trying to read a usb register Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx5/clock-mx51-mx53.c')
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c45
1 files changed, 43 insertions, 2 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 9fc65bbc9d77..2f9eae213094 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -954,6 +954,41 @@ static struct clk usboh3_clk = {
954 .parent = &pll2_sw_clk, 954 .parent = &pll2_sw_clk,
955 .get_rate = clk_usboh3_get_rate, 955 .get_rate = clk_usboh3_get_rate,
956 .set_parent = clk_usboh3_set_parent, 956 .set_parent = clk_usboh3_set_parent,
957 .enable = _clk_ccgr_enable,
958 .disable = _clk_ccgr_disable,
959 .enable_reg = MXC_CCM_CCGR2,
960 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
961};
962
963static struct clk usb_ahb_clk = {
964 .parent = &ipg_clk,
965 .enable = _clk_ccgr_enable,
966 .disable = _clk_ccgr_disable,
967 .enable_reg = MXC_CCM_CCGR2,
968 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
969};
970
971static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
972{
973 u32 reg;
974
975 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
976
977 if (parent == &pll3_sw_clk)
978 reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
979
980 __raw_writel(reg, MXC_CCM_CSCMR1);
981
982 return 0;
983}
984
985static struct clk usb_phy1_clk = {
986 .parent = &pll3_sw_clk,
987 .set_parent = clk_usb_phy1_set_parent,
988 .enable = _clk_ccgr_enable,
989 .enable_reg = MXC_CCM_CCGR2,
990 .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
991 .disable = _clk_ccgr_disable,
957}; 992};
958 993
959/* eCSPI */ 994/* eCSPI */
@@ -1094,9 +1129,12 @@ static struct clk_lookup mx51_lookups[] = {
1094 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) 1129 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1095 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) 1130 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
1096 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) 1131 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
1097 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) 1132 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
1133 _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
1098 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) 1134 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
1099 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) 1135 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
1136 _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
1137 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
1100 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) 1138 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1101 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) 1139 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1102 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) 1140 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
@@ -1170,6 +1208,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1170 mx51_revision(); 1208 mx51_revision();
1171 clk_disable(&iim_clk); 1209 clk_disable(&iim_clk);
1172 1210
1211 /* move usb_phy_clk to 24MHz */
1212 clk_set_parent(&usb_phy1_clk, &osc_clk);
1213
1173 /* set the usboh3_clk parent to pll2_sw_clk */ 1214 /* set the usboh3_clk parent to pll2_sw_clk */
1174 clk_set_parent(&usboh3_clk, &pll2_sw_clk); 1215 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1175 1216