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authorYong Shen <yong.shen@freescale.com>2011-01-10 07:08:54 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2011-01-11 04:07:14 -0500
commit2cad26a9d583ea16bb23a8cdc2f7a7df4662a72c (patch)
treec819d0205d256ea69f433458b83f06a7d8682682 /arch/arm/mach-mx5/clock-mx51-mx53.c
parentb0a6ba5ffbb52b5e8fccd1a013e770e1b0af03ba (diff)
ARM i.MX5 uart clock bug fix
uart clk is from pll3 on mx53 instead of mx51 Signed-off-by: Yong Shen <yong.shen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx5/clock-mx51-mx53.c')
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 64fe24900a4d..8f142294e10e 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1370,7 +1370,6 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1370 1370
1371 clk_tree_init(); 1371 clk_tree_init();
1372 1372
1373 clk_set_parent(&uart_root_clk, &pll3_sw_clk);
1374 clk_enable(&cpu_clk); 1373 clk_enable(&cpu_clk);
1375 clk_enable(&main_bus_clk); 1374 clk_enable(&main_bus_clk);
1376 1375
@@ -1413,6 +1412,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1413 1412
1414 clk_tree_init(); 1413 clk_tree_init();
1415 1414
1415 clk_set_parent(&uart_root_clk, &pll3_sw_clk);
1416 clk_enable(&cpu_clk); 1416 clk_enable(&cpu_clk);
1417 clk_enable(&main_bus_clk); 1417 clk_enable(&main_bus_clk);
1418 1418