diff options
author | Fabio Estevam <fabio.estevam@freescale.com> | 2010-12-13 07:47:05 -0500 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-12-14 03:55:53 -0500 |
commit | 28a4f908acb342350b9ecbfcdf0a999cb83e05aa (patch) | |
tree | ce0bea69a22fe4731a094a443d6ea2660a27c82b /arch/arm/mach-mx5/board-mx51_babbage.c | |
parent | bb477de2efc560e55c4a830329273661f3664bc8 (diff) |
ARM: mx5: check for error in ioremap
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx5/board-mx51_babbage.c')
-rw-r--r-- | arch/arm/mach-mx5/board-mx51_babbage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index a896f84895ad..368a315e9ace 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c | |||
@@ -262,6 +262,8 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
262 | void __iomem *usbother_base; | 262 | void __iomem *usbother_base; |
263 | 263 | ||
264 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 264 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
265 | if (!usb_base) | ||
266 | return -ENOMEM; | ||
265 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 267 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
266 | 268 | ||
267 | /* Set the PHY clock to 19.2MHz */ | 269 | /* Set the PHY clock to 19.2MHz */ |
@@ -280,6 +282,8 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
280 | void __iomem *usbother_base; | 282 | void __iomem *usbother_base; |
281 | 283 | ||
282 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 284 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
285 | if (!usb_base) | ||
286 | return -ENOMEM; | ||
283 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 287 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
284 | 288 | ||
285 | /* The clock for the USBH1 ULPI port will come externally from the PHY. */ | 289 | /* The clock for the USBH1 ULPI port will come externally from the PHY. */ |