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authorArnaud Patard (Rtp) <arnaud.patard@rtp-net.org>2010-11-26 09:20:52 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2010-12-03 05:05:16 -0500
commit96886c4361f1ae3f6c775d7c9295e2d557101d0f (patch)
treef3101c9303ed759ab5660985291366619a8e8fd9 /arch/arm/mach-mx5/board-cpuimx51sd.c
parentb99545cb59dc0a55507100a1335f4fd0ed521032 (diff)
iMX51: introduce IMX_GPIO_NR
Currently, to define a GPIO number, we're using something like : #define EFIKAMX_PCBID0 (2*32 + 16) to define GPIO 3 16. This is not really readable and it's error prone imho (note the 3 vs 2). So, I'm introducing a new macro to define this in a better way. Now, the code sample become : #define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) v2: - move to gpio.h - add parens & spaces - switch to IMX_GPIO_NR instead of MX51_GPIO_NR Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Eric BĂ©nard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx5/board-cpuimx51sd.c')
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index ff1f45e96c32..8e71c19b9019 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -43,19 +43,19 @@
43#include "devices-imx51.h" 43#include "devices-imx51.h"
44#include "devices.h" 44#include "devices.h"
45 45
46#define USBH1_RST (1*32 + 28) 46#define USBH1_RST IMX_GPIO_NR(2, 28)
47#define ETH_RST (1*32 + 31) 47#define ETH_RST IMX_GPIO_NR(2, 31)
48#define TSC2007_IRQGPIO (2*32 + 12) 48#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
49#define CAN_IRQGPIO (0*32 + 1) 49#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
50#define CAN_RST (3*32 + 15) 50#define CAN_RST IMX_GPIO_NR(4, 15)
51#define CAN_NCS (3*32 + 24) 51#define CAN_NCS IMX_GPIO_NR(4, 24)
52#define CAN_RXOBF (0*32 + 4) 52#define CAN_RXOBF IMX_GPIO_NR(1, 4)
53#define CAN_RX1BF (0*32 + 6) 53#define CAN_RX1BF IMX_GPIO_NR(1, 6)
54#define CAN_TXORTS (0*32 + 7) 54#define CAN_TXORTS IMX_GPIO_NR(1, 7)
55#define CAN_TX1RTS (0*32 + 8) 55#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
56#define CAN_TX2RTS (0*32 + 9) 56#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
57#define I2C_SCL (3*32 + 16) 57#define I2C_SCL IMX_GPIO_NR(4, 16)
58#define I2C_SDA (3*32 + 17) 58#define I2C_SDA IMX_GPIO_NR(4, 17)
59 59
60/* USB_CTRL_1 */ 60/* USB_CTRL_1 */
61#define MX51_USB_CTRL_1_OFFSET 0x10 61#define MX51_USB_CTRL_1_OFFSET 0x10
@@ -243,7 +243,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
243 .mode = SPI_MODE_0, 243 .mode = SPI_MODE_0,
244 .chip_select = 0, 244 .chip_select = 0,
245 .platform_data = &mcp251x_info, 245 .platform_data = &mcp251x_info,
246 .irq = gpio_to_irq(0 * 32 + 1) 246 .irq = gpio_to_irq(CAN_IRQGPIO)
247 }, 247 },
248}; 248};
249 249