diff options
author | Fabio Estevam <fabio.estevam@freescale.com> | 2010-12-13 07:47:05 -0500 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-12-14 03:55:53 -0500 |
commit | 28a4f908acb342350b9ecbfcdf0a999cb83e05aa (patch) | |
tree | ce0bea69a22fe4731a094a443d6ea2660a27c82b /arch/arm/mach-mx5/board-cpuimx51sd.c | |
parent | bb477de2efc560e55c4a830329273661f3664bc8 (diff) |
ARM: mx5: check for error in ioremap
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx5/board-cpuimx51sd.c')
-rw-r--r-- | arch/arm/mach-mx5/board-cpuimx51sd.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index 8e71c19b9019..7e8fb82d22fc 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c | |||
@@ -157,6 +157,8 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
157 | void __iomem *usbother_base; | 157 | void __iomem *usbother_base; |
158 | 158 | ||
159 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 159 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
160 | if (!usb_base) | ||
161 | return -ENOMEM; | ||
160 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 162 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
161 | 163 | ||
162 | /* Set the PHY clock to 19.2MHz */ | 164 | /* Set the PHY clock to 19.2MHz */ |
@@ -175,6 +177,8 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
175 | void __iomem *usbother_base; | 177 | void __iomem *usbother_base; |
176 | 178 | ||
177 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 179 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
180 | if (!usb_base) | ||
181 | return -ENOMEM; | ||
178 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 182 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
179 | 183 | ||
180 | /* The clock for the USBH1 ULPI port will come from the PHY. */ | 184 | /* The clock for the USBH1 ULPI port will come from the PHY. */ |