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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-10-22 08:49:45 -0400
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-11-17 02:57:22 -0500
commit9651b7db59893e796dfdd170485543b9863be9d8 (patch)
tree68e2d969b2fa2dd447fcb5fad994fc811d0c7980 /arch/arm/mach-mx3/mm.c
parentbe6786ac738801d39cfd264ec88c352efd029578 (diff)
ARM: mx3: fix the last users of IMX_NEEDS_DEPRECATED_SYMBOLS
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx3/mm.c')
-rw-r--r--arch/arm/mach-mx3/mm.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index b4ffc531a82c..809ee40b9f0e 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -42,29 +42,29 @@
42 */ 42 */
43static struct map_desc mxc_io_desc[] __initdata = { 43static struct map_desc mxc_io_desc[] __initdata = {
44 { 44 {
45 .virtual = X_MEMC_BASE_ADDR_VIRT, 45 .virtual = MX3x_X_MEMC_BASE_ADDR_VIRT,
46 .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), 46 .pfn = __phys_to_pfn(MX3x_X_MEMC_BASE_ADDR),
47 .length = X_MEMC_SIZE, 47 .length = MX3x_X_MEMC_SIZE,
48 .type = MT_DEVICE 48 .type = MT_DEVICE
49 }, { 49 }, {
50 .virtual = AVIC_BASE_ADDR_VIRT, 50 .virtual = MX3x_AVIC_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(AVIC_BASE_ADDR), 51 .pfn = __phys_to_pfn(MX3x_AVIC_BASE_ADDR),
52 .length = AVIC_SIZE, 52 .length = MX3x_AVIC_SIZE,
53 .type = MT_DEVICE_NONSHARED 53 .type = MT_DEVICE_NONSHARED
54 }, { 54 }, {
55 .virtual = AIPS1_BASE_ADDR_VIRT, 55 .virtual = MX3x_AIPS1_BASE_ADDR_VIRT,
56 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), 56 .pfn = __phys_to_pfn(MX3x_AIPS1_BASE_ADDR),
57 .length = AIPS1_SIZE, 57 .length = MX3x_AIPS1_SIZE,
58 .type = MT_DEVICE_NONSHARED 58 .type = MT_DEVICE_NONSHARED
59 }, { 59 }, {
60 .virtual = AIPS2_BASE_ADDR_VIRT, 60 .virtual = MX3x_AIPS2_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), 61 .pfn = __phys_to_pfn(MX3x_AIPS2_BASE_ADDR),
62 .length = AIPS2_SIZE, 62 .length = MX3x_AIPS2_SIZE,
63 .type = MT_DEVICE_NONSHARED 63 .type = MT_DEVICE_NONSHARED
64 }, { 64 }, {
65 .virtual = SPBA0_BASE_ADDR_VIRT, 65 .virtual = MX3x_SPBA0_BASE_ADDR_VIRT,
66 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), 66 .pfn = __phys_to_pfn(MX3x_SPBA0_BASE_ADDR),
67 .length = SPBA0_SIZE, 67 .length = MX3x_SPBA0_SIZE,
68 .type = MT_DEVICE_NONSHARED 68 .type = MT_DEVICE_NONSHARED
69 }, 69 },
70}; 70};
@@ -77,7 +77,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
77void __init mx31_map_io(void) 77void __init mx31_map_io(void)
78{ 78{
79 mxc_set_cpu_type(MXC_CPU_MX31); 79 mxc_set_cpu_type(MXC_CPU_MX31);
80 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); 80 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
81 81
82 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 82 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
83} 83}
@@ -86,8 +86,8 @@ void __init mx31_map_io(void)
86void __init mx35_map_io(void) 86void __init mx35_map_io(void)
87{ 87{
88 mxc_set_cpu_type(MXC_CPU_MX35); 88 mxc_set_cpu_type(MXC_CPU_MX35);
89 mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); 89 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
90 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); 90 mxc_arch_reset_init(MX35_IO_ADDRESS(MX3x_WDOG_BASE_ADDR));
91 91
92 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 92 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
93} 93}
@@ -97,7 +97,7 @@ int imx3x_register_gpios(void);
97 97
98void __init mx31_init_irq(void) 98void __init mx31_init_irq(void)
99{ 99{
100 mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); 100 mxc_init_irq(MX31_IO_ADDRESS(MX3x_AVIC_BASE_ADDR));
101 imx3x_register_gpios(); 101 imx3x_register_gpios();
102} 102}
103 103
@@ -129,7 +129,7 @@ static int mxc_init_l2x0(void)
129 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); 129 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
130 } 130 }
131 131
132 l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); 132 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
133 if (IS_ERR(l2x0_base)) { 133 if (IS_ERR(l2x0_base)) {
134 printk(KERN_ERR "remapping L2 cache area failed with %ld\n", 134 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
135 PTR_ERR(l2x0_base)); 135 PTR_ERR(l2x0_base));