mx31: rework of iomux support

This new implemenatation avoids that two physical pins are claimed by
the same driver (also with the the gpr hardware modes).
The gpio kernel lib is also called when a capable gpio pin is assigned
its gpio function.
The mxc_iomux_mode function is still here for backward compatibility but
should not be used anymore.

V2:

In the precendent revision, the iomux code was claiming a pin when its
hardware mode was changed. This was uncorrect: when the hardware mode is
changed, the pin must still be claimed through the iomux.

In order to have a pin working in mode hw2, we must fist issue the
mxc_iomux_set_gpr call and then the corresponding mxc_iomux_mode calls
with the FUNC mode (usually done with mxc_iomux_setup_multiple_pins).
The reverse calls must be done to fee the pins.

Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 84 insertions, 4 deletions

diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
index 7a5088b519a8..40ffc5a664d9 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux.c
@@ -1,6 +1,7 @@
 /*
  * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -21,6 +22,7 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/kernel.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 #include <mach/iomux-mx3.h>
@@ -38,6 +40,8 @@
 static DEFINE_SPINLOCK(gpio_mux_lock);
 
 #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
+
+unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
 /*
  * set the mode for a IOMUX pin.
  */
@@ -50,9 +54,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
         field = pin_mode & 0x3;
         mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
 
-        pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
-                        __func__, (pin_mode & IOMUX_REG_MASK), field, mode);
-
         spin_lock(&gpio_mux_lock);
 
         l = __raw_readl(reg);
@@ -93,6 +94,86 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
 EXPORT_SYMBOL(mxc_iomux_set_pad);
 
 /*
+ * setups a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
+ */
+int mxc_iomux_setup_pin(const unsigned int pin, const char *label)
+{
+        unsigned pad = pin & IOMUX_PADNUM_MASK;
+        unsigned gpio;
+
+        if (pad >= (PIN_MAX + 1)) {
+                printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
+                        pad, label ? label : "?");
+                return -EINVAL;
+        }
+
+        if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
+                printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
+                        pad, label ? label : "?");
+                return -EINVAL;
+        }
+        mxc_iomux_mode(pin);
+
+        /* if we have a gpio, we can allocate it */
+        gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT;
+        if (gpio < (GPIO_PORT_MAX + 1) * 32)
+                if (gpio_request(gpio, label))
+                        return -EINVAL;
+
+        return 0;
+}
+EXPORT_SYMBOL(mxc_iomux_setup_pin);
+
+int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+                const char *label)
+{
+        unsigned int *p = pin_list;
+        int i;
+        int ret = -EINVAL;
+
+        for (i = 0; i < count; i++) {
+                if (mxc_iomux_setup_pin(*p, label))
+                        goto setup_error;
+                p++;
+        }
+        return 0;
+
+setup_error:
+        mxc_iomux_release_multiple_pins(pin_list, i);
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
+
+void mxc_iomux_release_pin(const unsigned int pin)
+{
+        unsigned pad = pin & IOMUX_PADNUM_MASK;
+        unsigned gpio;
+
+        if (pad < (PIN_MAX + 1))
+                clear_bit(pad, mxc_pin_alloc_map);
+
+        gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT;
+        if (gpio < (GPIO_PORT_MAX + 1) * 32)
+                gpio_free(gpio);
+}
+EXPORT_SYMBOL(mxc_iomux_release_pin);
+
+void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
+{
+        unsigned int *p = pin_list;
+        int i;
+
+        for (i = 0; i < count; i++) {
+                mxc_iomux_release_pin(*p);
+                p++;
+        }
+}
+EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
+
+/*
  * This function enables/disables the general purpose function for a particular
  * signal.
  */
@@ -111,4 +192,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
         spin_unlock(&gpio_mux_lock);
 }
 EXPORT_SYMBOL(mxc_iomux_set_gpr);
-