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authorSascha Hauer <s.hauer@pengutronix.de>2008-07-05 04:02:50 -0400
committerRobert Schwebel <r.schwebel@pengutronix.de>2008-07-05 04:02:50 -0400
commit90292ea60f1c730efb9fea02b2e12676da89ebef (patch)
tree514a820eca32b08b79864aeb5382d620d37b5d99 /arch/arm/mach-mx3/iomux.c
parent07bd1a6cc7cbb3f373fbe49b204c6cde5e9155fc (diff)
MXC: add io multiplexing functions for mx3
This patch adds functions to use the io multiplexer on mx3 platforms. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx3/iomux.c')
-rw-r--r--arch/arm/mach-mx3/iomux.c111
1 files changed, 111 insertions, 0 deletions
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
new file mode 100644
index 000000000000..adc51feefc1d
--- /dev/null
+++ b/arch/arm/mach-mx3/iomux.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/spinlock.h>
22#include <linux/io.h>
23#include <linux/gpio.h>
24#include <asm/hardware.h>
25#include <asm/arch/gpio.h>
26#include <asm/arch/iomux-mx3.h>
27
28/*
29 * IOMUX register (base) addresses
30 */
31#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR)
32#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
33#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
34#define IOMUXGPR (IOMUX_BASE + 0x008)
35#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
36#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
37
38static DEFINE_SPINLOCK(gpio_mux_lock);
39
40#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
41/*
42 * set the mode for a IOMUX pin.
43 */
44int mxc_iomux_mode(unsigned int pin_mode)
45{
46 u32 reg, field, l, mode, ret = 0;
47
48 reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
49 field = pin_mode & 0x3;
50 mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
51
52 pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
53 __func__, (pin_mode & IOMUX_REG_MASK), field, mode);
54
55 spin_lock(&gpio_mux_lock);
56
57 l = __raw_readl(reg);
58 l &= ~(0xff << (field * 8));
59 l |= mode << (field * 8);
60 __raw_writel(l, reg);
61
62 spin_unlock(&gpio_mux_lock);
63
64 return ret;
65}
66EXPORT_SYMBOL(mxc_iomux_mode);
67
68/*
69 * This function configures the pad value for a IOMUX pin.
70 */
71void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
72{
73 u32 reg, field, l;
74
75 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
76 field = (pin + 2) % 3;
77
78 pr_debug("%s: reg offset = 0x%x field = %d\n",
79 __func__, (pin + 2) / 3, field);
80
81 spin_lock(&gpio_mux_lock);
82
83 l = __raw_readl(reg);
84 l &= ~(0x1ff << (field * 9));
85 l |= config << (field * 9);
86 __raw_writel(l, reg);
87
88 spin_unlock(&gpio_mux_lock);
89}
90EXPORT_SYMBOL(mxc_iomux_set_pad);
91
92/*
93 * This function enables/disables the general purpose function for a particular
94 * signal.
95 */
96void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
97{
98 u32 l;
99
100 spin_lock(&gpio_mux_lock);
101 l = __raw_readl(IOMUXGPR);
102 if (en)
103 l |= gp;
104 else
105 l &= ~gp;
106
107 __raw_writel(l, IOMUXGPR);
108 spin_unlock(&gpio_mux_lock);
109}
110EXPORT_SYMBOL(mxc_iomux_set_gpr);
111