diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-10-22 08:49:45 -0400 |
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committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-11-17 02:57:22 -0500 |
commit | 9651b7db59893e796dfdd170485543b9863be9d8 (patch) | |
tree | 68e2d969b2fa2dd447fcb5fad994fc811d0c7980 /arch/arm/mach-mx3/devices.c | |
parent | be6786ac738801d39cfd264ec88c352efd029578 (diff) |
ARM: mx3: fix the last users of IMX_NEEDS_DEPRECATED_SYMBOLS
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx3/devices.c')
-rw-r--r-- | arch/arm/mach-mx3/devices.c | 69 |
1 files changed, 37 insertions, 32 deletions
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index d4da9496089a..74f74f4fcff0 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c | |||
@@ -33,18 +33,18 @@ | |||
33 | static struct mxc_gpio_port imx_gpio_ports[] = { | 33 | static struct mxc_gpio_port imx_gpio_ports[] = { |
34 | { | 34 | { |
35 | .chip.label = "gpio-0", | 35 | .chip.label = "gpio-0", |
36 | .base = IO_ADDRESS(GPIO1_BASE_ADDR), | 36 | .base = MX31_IO_ADDRESS(MX31_GPIO1_BASE_ADDR), |
37 | .irq = MXC_INT_GPIO1, | 37 | .irq = MX3x_INT_GPIO1, |
38 | .virtual_irq_start = MXC_GPIO_IRQ_START, | 38 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
39 | }, { | 39 | }, { |
40 | .chip.label = "gpio-1", | 40 | .chip.label = "gpio-1", |
41 | .base = IO_ADDRESS(GPIO2_BASE_ADDR), | 41 | .base = MX31_IO_ADDRESS(MX31_GPIO2_BASE_ADDR), |
42 | .irq = MXC_INT_GPIO2, | 42 | .irq = MX3x_INT_GPIO2, |
43 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | 43 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
44 | }, { | 44 | }, { |
45 | .chip.label = "gpio-2", | 45 | .chip.label = "gpio-2", |
46 | .base = IO_ADDRESS(GPIO3_BASE_ADDR), | 46 | .base = MX31_IO_ADDRESS(MX31_GPIO3_BASE_ADDR), |
47 | .irq = MXC_INT_GPIO3, | 47 | .irq = MX3x_INT_GPIO3, |
48 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | 48 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
49 | } | 49 | } |
50 | }; | 50 | }; |
@@ -56,8 +56,8 @@ int __init imx3x_register_gpios(void) | |||
56 | 56 | ||
57 | static struct resource mxc_w1_master_resources[] = { | 57 | static struct resource mxc_w1_master_resources[] = { |
58 | { | 58 | { |
59 | .start = OWIRE_BASE_ADDR, | 59 | .start = MX3x_OWIRE_BASE_ADDR, |
60 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | 60 | .end = MX3x_OWIRE_BASE_ADDR + SZ_4K - 1, |
61 | .flags = IORESOURCE_MEM, | 61 | .flags = IORESOURCE_MEM, |
62 | }, | 62 | }, |
63 | }; | 63 | }; |
@@ -110,8 +110,8 @@ struct platform_device mxcsdhc_device1 = { | |||
110 | 110 | ||
111 | static struct resource rnga_resources[] = { | 111 | static struct resource rnga_resources[] = { |
112 | { | 112 | { |
113 | .start = RNGA_BASE_ADDR, | 113 | .start = MX3x_RNGA_BASE_ADDR, |
114 | .end = RNGA_BASE_ADDR + 0x28, | 114 | .end = MX3x_RNGA_BASE_ADDR + 0x28, |
115 | .flags = IORESOURCE_MEM, | 115 | .flags = IORESOURCE_MEM, |
116 | }, | 116 | }, |
117 | }; | 117 | }; |
@@ -129,20 +129,20 @@ struct platform_device mxc_rnga_device = { | |||
129 | /* The resource order is important! */ | 129 | /* The resource order is important! */ |
130 | static struct resource mx3_ipu_rsrc[] = { | 130 | static struct resource mx3_ipu_rsrc[] = { |
131 | { | 131 | { |
132 | .start = IPU_CTRL_BASE_ADDR, | 132 | .start = MX3x_IPU_CTRL_BASE_ADDR, |
133 | .end = IPU_CTRL_BASE_ADDR + 0x5F, | 133 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F, |
134 | .flags = IORESOURCE_MEM, | 134 | .flags = IORESOURCE_MEM, |
135 | }, { | 135 | }, { |
136 | .start = IPU_CTRL_BASE_ADDR + 0x88, | 136 | .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88, |
137 | .end = IPU_CTRL_BASE_ADDR + 0xB3, | 137 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3, |
138 | .flags = IORESOURCE_MEM, | 138 | .flags = IORESOURCE_MEM, |
139 | }, { | 139 | }, { |
140 | .start = MXC_INT_IPU_SYN, | 140 | .start = MX3x_INT_IPU_SYN, |
141 | .end = MXC_INT_IPU_SYN, | 141 | .end = MX3x_INT_IPU_SYN, |
142 | .flags = IORESOURCE_IRQ, | 142 | .flags = IORESOURCE_IRQ, |
143 | }, { | 143 | }, { |
144 | .start = MXC_INT_IPU_ERR, | 144 | .start = MX3x_INT_IPU_ERR, |
145 | .end = MXC_INT_IPU_ERR, | 145 | .end = MX3x_INT_IPU_ERR, |
146 | .flags = IORESOURCE_IRQ, | 146 | .flags = IORESOURCE_IRQ, |
147 | }, | 147 | }, |
148 | }; | 148 | }; |
@@ -156,8 +156,8 @@ struct platform_device mx3_ipu = { | |||
156 | 156 | ||
157 | static struct resource fb_resources[] = { | 157 | static struct resource fb_resources[] = { |
158 | { | 158 | { |
159 | .start = IPU_CTRL_BASE_ADDR + 0xB4, | 159 | .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4, |
160 | .end = IPU_CTRL_BASE_ADDR + 0x1BF, | 160 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF, |
161 | .flags = IORESOURCE_MEM, | 161 | .flags = IORESOURCE_MEM, |
162 | }, | 162 | }, |
163 | }; | 163 | }; |
@@ -174,8 +174,8 @@ struct platform_device mx3_fb = { | |||
174 | 174 | ||
175 | static struct resource camera_resources[] = { | 175 | static struct resource camera_resources[] = { |
176 | { | 176 | { |
177 | .start = IPU_CTRL_BASE_ADDR + 0x60, | 177 | .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60, |
178 | .end = IPU_CTRL_BASE_ADDR + 0x87, | 178 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87, |
179 | .flags = IORESOURCE_MEM, | 179 | .flags = IORESOURCE_MEM, |
180 | }, | 180 | }, |
181 | }; | 181 | }; |
@@ -196,8 +196,8 @@ static struct resource otg_resources[] = { | |||
196 | .end = MX31_OTG_BASE_ADDR + 0x1ff, | 196 | .end = MX31_OTG_BASE_ADDR + 0x1ff, |
197 | .flags = IORESOURCE_MEM, | 197 | .flags = IORESOURCE_MEM, |
198 | }, { | 198 | }, { |
199 | .start = MXC_INT_USB3, | 199 | .start = MX31_INT_USB3, |
200 | .end = MXC_INT_USB3, | 200 | .end = MX31_INT_USB3, |
201 | .flags = IORESOURCE_IRQ, | 201 | .flags = IORESOURCE_IRQ, |
202 | }, | 202 | }, |
203 | }; | 203 | }; |
@@ -238,8 +238,8 @@ static struct resource mxc_usbh1_resources[] = { | |||
238 | .end = MX31_OTG_BASE_ADDR + 0x3ff, | 238 | .end = MX31_OTG_BASE_ADDR + 0x3ff, |
239 | .flags = IORESOURCE_MEM, | 239 | .flags = IORESOURCE_MEM, |
240 | }, { | 240 | }, { |
241 | .start = MXC_INT_USB1, | 241 | .start = MX31_INT_USB1, |
242 | .end = MXC_INT_USB1, | 242 | .end = MX31_INT_USB1, |
243 | .flags = IORESOURCE_IRQ, | 243 | .flags = IORESOURCE_IRQ, |
244 | }, | 244 | }, |
245 | }; | 245 | }; |
@@ -255,6 +255,7 @@ struct platform_device mxc_usbh1 = { | |||
255 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | 255 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), |
256 | }; | 256 | }; |
257 | 257 | ||
258 | #ifdef CONFIG_ARCH_MX31 | ||
258 | /* USB host 2 */ | 259 | /* USB host 2 */ |
259 | static u64 usbh2_dmamask = ~(u32)0; | 260 | static u64 usbh2_dmamask = ~(u32)0; |
260 | 261 | ||
@@ -264,8 +265,8 @@ static struct resource mxc_usbh2_resources[] = { | |||
264 | .end = MX31_OTG_BASE_ADDR + 0x5ff, | 265 | .end = MX31_OTG_BASE_ADDR + 0x5ff, |
265 | .flags = IORESOURCE_MEM, | 266 | .flags = IORESOURCE_MEM, |
266 | }, { | 267 | }, { |
267 | .start = MXC_INT_USB2, | 268 | .start = MX31_INT_USB2, |
268 | .end = MXC_INT_USB2, | 269 | .end = MX31_INT_USB2, |
269 | .flags = IORESOURCE_IRQ, | 270 | .flags = IORESOURCE_IRQ, |
270 | }, | 271 | }, |
271 | }; | 272 | }; |
@@ -280,6 +281,7 @@ struct platform_device mxc_usbh2 = { | |||
280 | .resource = mxc_usbh2_resources, | 281 | .resource = mxc_usbh2_resources, |
281 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | 282 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), |
282 | }; | 283 | }; |
284 | #endif | ||
283 | 285 | ||
284 | static struct resource imx_wdt_resources[] = { | 286 | static struct resource imx_wdt_resources[] = { |
285 | { | 287 | { |
@@ -343,14 +345,17 @@ static int __init mx3_devices_init(void) | |||
343 | #endif | 345 | #endif |
344 | #if defined(CONFIG_ARCH_MX35) | 346 | #if defined(CONFIG_ARCH_MX35) |
345 | if (cpu_is_mx35()) { | 347 | if (cpu_is_mx35()) { |
348 | imx_gpio_ports[0].base = MX35_IO_ADDRESS(MX35_GPIO1_BASE_ADDR), | ||
349 | imx_gpio_ports[1].base = MX35_IO_ADDRESS(MX35_GPIO2_BASE_ADDR), | ||
350 | imx_gpio_ports[2].base = MX35_IO_ADDRESS(MX35_GPIO3_BASE_ADDR), | ||
346 | otg_resources[0].start = MX35_OTG_BASE_ADDR; | 351 | otg_resources[0].start = MX35_OTG_BASE_ADDR; |
347 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; | 352 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; |
348 | otg_resources[1].start = MXC_INT_USBOTG; | 353 | otg_resources[1].start = MX35_INT_USBOTG; |
349 | otg_resources[1].end = MXC_INT_USBOTG; | 354 | otg_resources[1].end = MX35_INT_USBOTG; |
350 | mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; | 355 | mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; |
351 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; | 356 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; |
352 | mxc_usbh1_resources[1].start = MXC_INT_USBHS; | 357 | mxc_usbh1_resources[1].start = MX35_INT_USBHS; |
353 | mxc_usbh1_resources[1].end = MXC_INT_USBHS; | 358 | mxc_usbh1_resources[1].end = MX35_INT_USBHS; |
354 | imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; | 359 | imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; |
355 | imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; | 360 | imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; |
356 | } | 361 | } |