diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-31 09:20:16 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-31 09:20:16 -0400 |
commit | 7b70c4275f28702b76b273c8534c38f8313812e9 (patch) | |
tree | 1df2229ca02466bd1adda814ac5c37aa0a597db1 /arch/arm/mach-mx3/devices.c | |
parent | ceb0885d3b01bb2e2f18765770e212914f2864be (diff) | |
parent | a20df564d15bd28e3df24e1c65b885bd74d23f17 (diff) |
Merge branch 'devel-stable' into devel
Conflicts:
arch/arm/kernel/entry-armv.S
arch/arm/kernel/setup.c
arch/arm/mm/init.c
Diffstat (limited to 'arch/arm/mach-mx3/devices.c')
-rw-r--r-- | arch/arm/mach-mx3/devices.c | 247 |
1 files changed, 6 insertions, 241 deletions
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index db7acd6e9101..a4fd1a26fc91 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c | |||
@@ -25,108 +25,10 @@ | |||
25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
26 | #include <mach/irqs.h> | 26 | #include <mach/irqs.h> |
27 | #include <mach/common.h> | 27 | #include <mach/common.h> |
28 | #include <mach/imx-uart.h> | ||
29 | #include <mach/mx3_camera.h> | 28 | #include <mach/mx3_camera.h> |
30 | 29 | ||
31 | #include "devices.h" | 30 | #include "devices.h" |
32 | 31 | ||
33 | static struct resource uart0[] = { | ||
34 | { | ||
35 | .start = UART1_BASE_ADDR, | ||
36 | .end = UART1_BASE_ADDR + 0x0B5, | ||
37 | .flags = IORESOURCE_MEM, | ||
38 | }, { | ||
39 | .start = MXC_INT_UART1, | ||
40 | .end = MXC_INT_UART1, | ||
41 | .flags = IORESOURCE_IRQ, | ||
42 | }, | ||
43 | }; | ||
44 | |||
45 | struct platform_device mxc_uart_device0 = { | ||
46 | .name = "imx-uart", | ||
47 | .id = 0, | ||
48 | .resource = uart0, | ||
49 | .num_resources = ARRAY_SIZE(uart0), | ||
50 | }; | ||
51 | |||
52 | static struct resource uart1[] = { | ||
53 | { | ||
54 | .start = UART2_BASE_ADDR, | ||
55 | .end = UART2_BASE_ADDR + 0x0B5, | ||
56 | .flags = IORESOURCE_MEM, | ||
57 | }, { | ||
58 | .start = MXC_INT_UART2, | ||
59 | .end = MXC_INT_UART2, | ||
60 | .flags = IORESOURCE_IRQ, | ||
61 | }, | ||
62 | }; | ||
63 | |||
64 | struct platform_device mxc_uart_device1 = { | ||
65 | .name = "imx-uart", | ||
66 | .id = 1, | ||
67 | .resource = uart1, | ||
68 | .num_resources = ARRAY_SIZE(uart1), | ||
69 | }; | ||
70 | |||
71 | static struct resource uart2[] = { | ||
72 | { | ||
73 | .start = UART3_BASE_ADDR, | ||
74 | .end = UART3_BASE_ADDR + 0x0B5, | ||
75 | .flags = IORESOURCE_MEM, | ||
76 | }, { | ||
77 | .start = MXC_INT_UART3, | ||
78 | .end = MXC_INT_UART3, | ||
79 | .flags = IORESOURCE_IRQ, | ||
80 | }, | ||
81 | }; | ||
82 | |||
83 | struct platform_device mxc_uart_device2 = { | ||
84 | .name = "imx-uart", | ||
85 | .id = 2, | ||
86 | .resource = uart2, | ||
87 | .num_resources = ARRAY_SIZE(uart2), | ||
88 | }; | ||
89 | |||
90 | #ifdef CONFIG_ARCH_MX31 | ||
91 | static struct resource uart3[] = { | ||
92 | { | ||
93 | .start = UART4_BASE_ADDR, | ||
94 | .end = UART4_BASE_ADDR + 0x0B5, | ||
95 | .flags = IORESOURCE_MEM, | ||
96 | }, { | ||
97 | .start = MXC_INT_UART4, | ||
98 | .end = MXC_INT_UART4, | ||
99 | .flags = IORESOURCE_IRQ, | ||
100 | }, | ||
101 | }; | ||
102 | |||
103 | struct platform_device mxc_uart_device3 = { | ||
104 | .name = "imx-uart", | ||
105 | .id = 3, | ||
106 | .resource = uart3, | ||
107 | .num_resources = ARRAY_SIZE(uart3), | ||
108 | }; | ||
109 | |||
110 | static struct resource uart4[] = { | ||
111 | { | ||
112 | .start = UART5_BASE_ADDR, | ||
113 | .end = UART5_BASE_ADDR + 0x0B5, | ||
114 | .flags = IORESOURCE_MEM, | ||
115 | }, { | ||
116 | .start = MXC_INT_UART5, | ||
117 | .end = MXC_INT_UART5, | ||
118 | .flags = IORESOURCE_IRQ, | ||
119 | }, | ||
120 | }; | ||
121 | |||
122 | struct platform_device mxc_uart_device4 = { | ||
123 | .name = "imx-uart", | ||
124 | .id = 4, | ||
125 | .resource = uart4, | ||
126 | .num_resources = ARRAY_SIZE(uart4), | ||
127 | }; | ||
128 | #endif /* CONFIG_ARCH_MX31 */ | ||
129 | |||
130 | /* GPIO port description */ | 32 | /* GPIO port description */ |
131 | static struct mxc_gpio_port imx_gpio_ports[] = { | 33 | static struct mxc_gpio_port imx_gpio_ports[] = { |
132 | { | 34 | { |
@@ -147,7 +49,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = { | |||
147 | } | 49 | } |
148 | }; | 50 | }; |
149 | 51 | ||
150 | int __init mxc_register_gpios(void) | 52 | int __init imx3x_register_gpios(void) |
151 | { | 53 | { |
152 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | 54 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); |
153 | } | 55 | } |
@@ -167,82 +69,6 @@ struct platform_device mxc_w1_master_device = { | |||
167 | .resource = mxc_w1_master_resources, | 69 | .resource = mxc_w1_master_resources, |
168 | }; | 70 | }; |
169 | 71 | ||
170 | static struct resource mxc_nand_resources[] = { | ||
171 | { | ||
172 | .start = 0, /* runtime dependent */ | ||
173 | .end = 0, | ||
174 | .flags = IORESOURCE_MEM, | ||
175 | }, { | ||
176 | .start = MXC_INT_NANDFC, | ||
177 | .end = MXC_INT_NANDFC, | ||
178 | .flags = IORESOURCE_IRQ, | ||
179 | }, | ||
180 | }; | ||
181 | |||
182 | struct platform_device mxc_nand_device = { | ||
183 | .name = "mxc_nand", | ||
184 | .id = 0, | ||
185 | .num_resources = ARRAY_SIZE(mxc_nand_resources), | ||
186 | .resource = mxc_nand_resources, | ||
187 | }; | ||
188 | |||
189 | static struct resource mxc_i2c0_resources[] = { | ||
190 | { | ||
191 | .start = I2C_BASE_ADDR, | ||
192 | .end = I2C_BASE_ADDR + SZ_4K - 1, | ||
193 | .flags = IORESOURCE_MEM, | ||
194 | }, { | ||
195 | .start = MXC_INT_I2C, | ||
196 | .end = MXC_INT_I2C, | ||
197 | .flags = IORESOURCE_IRQ, | ||
198 | }, | ||
199 | }; | ||
200 | |||
201 | struct platform_device mxc_i2c_device0 = { | ||
202 | .name = "imx-i2c", | ||
203 | .id = 0, | ||
204 | .num_resources = ARRAY_SIZE(mxc_i2c0_resources), | ||
205 | .resource = mxc_i2c0_resources, | ||
206 | }; | ||
207 | |||
208 | static struct resource mxc_i2c1_resources[] = { | ||
209 | { | ||
210 | .start = I2C2_BASE_ADDR, | ||
211 | .end = I2C2_BASE_ADDR + SZ_4K - 1, | ||
212 | .flags = IORESOURCE_MEM, | ||
213 | }, { | ||
214 | .start = MXC_INT_I2C2, | ||
215 | .end = MXC_INT_I2C2, | ||
216 | .flags = IORESOURCE_IRQ, | ||
217 | }, | ||
218 | }; | ||
219 | |||
220 | struct platform_device mxc_i2c_device1 = { | ||
221 | .name = "imx-i2c", | ||
222 | .id = 1, | ||
223 | .num_resources = ARRAY_SIZE(mxc_i2c1_resources), | ||
224 | .resource = mxc_i2c1_resources, | ||
225 | }; | ||
226 | |||
227 | static struct resource mxc_i2c2_resources[] = { | ||
228 | { | ||
229 | .start = I2C3_BASE_ADDR, | ||
230 | .end = I2C3_BASE_ADDR + SZ_4K - 1, | ||
231 | .flags = IORESOURCE_MEM, | ||
232 | }, { | ||
233 | .start = MXC_INT_I2C3, | ||
234 | .end = MXC_INT_I2C3, | ||
235 | .flags = IORESOURCE_IRQ, | ||
236 | }, | ||
237 | }; | ||
238 | |||
239 | struct platform_device mxc_i2c_device2 = { | ||
240 | .name = "imx-i2c", | ||
241 | .id = 2, | ||
242 | .num_resources = ARRAY_SIZE(mxc_i2c2_resources), | ||
243 | .resource = mxc_i2c2_resources, | ||
244 | }; | ||
245 | |||
246 | #ifdef CONFIG_ARCH_MX31 | 72 | #ifdef CONFIG_ARCH_MX31 |
247 | static struct resource mxcsdhc0_resources[] = { | 73 | static struct resource mxcsdhc0_resources[] = { |
248 | { | 74 | { |
@@ -455,68 +281,7 @@ struct platform_device mxc_usbh2 = { | |||
455 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | 281 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), |
456 | }; | 282 | }; |
457 | 283 | ||
458 | /* | 284 | #if defined(CONFIG_ARCH_MX35) |
459 | * SPI master controller | ||
460 | * 3 channels | ||
461 | */ | ||
462 | static struct resource mxc_spi_0_resources[] = { | ||
463 | { | ||
464 | .start = CSPI1_BASE_ADDR, | ||
465 | .end = CSPI1_BASE_ADDR + SZ_4K - 1, | ||
466 | .flags = IORESOURCE_MEM, | ||
467 | }, { | ||
468 | .start = MXC_INT_CSPI1, | ||
469 | .end = MXC_INT_CSPI1, | ||
470 | .flags = IORESOURCE_IRQ, | ||
471 | }, | ||
472 | }; | ||
473 | |||
474 | static struct resource mxc_spi_1_resources[] = { | ||
475 | { | ||
476 | .start = CSPI2_BASE_ADDR, | ||
477 | .end = CSPI2_BASE_ADDR + SZ_4K - 1, | ||
478 | .flags = IORESOURCE_MEM, | ||
479 | }, { | ||
480 | .start = MXC_INT_CSPI2, | ||
481 | .end = MXC_INT_CSPI2, | ||
482 | .flags = IORESOURCE_IRQ, | ||
483 | }, | ||
484 | }; | ||
485 | |||
486 | static struct resource mxc_spi_2_resources[] = { | ||
487 | { | ||
488 | .start = CSPI3_BASE_ADDR, | ||
489 | .end = CSPI3_BASE_ADDR + SZ_4K - 1, | ||
490 | .flags = IORESOURCE_MEM, | ||
491 | }, { | ||
492 | .start = MXC_INT_CSPI3, | ||
493 | .end = MXC_INT_CSPI3, | ||
494 | .flags = IORESOURCE_IRQ, | ||
495 | }, | ||
496 | }; | ||
497 | |||
498 | struct platform_device mxc_spi_device0 = { | ||
499 | .name = "spi_imx", | ||
500 | .id = 0, | ||
501 | .num_resources = ARRAY_SIZE(mxc_spi_0_resources), | ||
502 | .resource = mxc_spi_0_resources, | ||
503 | }; | ||
504 | |||
505 | struct platform_device mxc_spi_device1 = { | ||
506 | .name = "spi_imx", | ||
507 | .id = 1, | ||
508 | .num_resources = ARRAY_SIZE(mxc_spi_1_resources), | ||
509 | .resource = mxc_spi_1_resources, | ||
510 | }; | ||
511 | |||
512 | struct platform_device mxc_spi_device2 = { | ||
513 | .name = "spi_imx", | ||
514 | .id = 2, | ||
515 | .num_resources = ARRAY_SIZE(mxc_spi_2_resources), | ||
516 | .resource = mxc_spi_2_resources, | ||
517 | }; | ||
518 | |||
519 | #ifdef CONFIG_ARCH_MX35 | ||
520 | static struct resource mxc_fec_resources[] = { | 285 | static struct resource mxc_fec_resources[] = { |
521 | { | 286 | { |
522 | .start = MXC_FEC_BASE_ADDR, | 287 | .start = MXC_FEC_BASE_ADDR, |
@@ -628,16 +393,15 @@ struct platform_device imx_kpp_device = { | |||
628 | 393 | ||
629 | static int __init mx3_devices_init(void) | 394 | static int __init mx3_devices_init(void) |
630 | { | 395 | { |
396 | #if defined(CONFIG_ARCH_MX31) | ||
631 | if (cpu_is_mx31()) { | 397 | if (cpu_is_mx31()) { |
632 | mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR; | ||
633 | mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff; | ||
634 | imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; | 398 | imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; |
635 | imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; | 399 | imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; |
636 | mxc_register_device(&mxc_rnga_device, NULL); | 400 | mxc_register_device(&mxc_rnga_device, NULL); |
637 | } | 401 | } |
402 | #endif | ||
403 | #if defined(CONFIG_ARCH_MX35) | ||
638 | if (cpu_is_mx35()) { | 404 | if (cpu_is_mx35()) { |
639 | mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; | ||
640 | mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff; | ||
641 | otg_resources[0].start = MX35_OTG_BASE_ADDR; | 405 | otg_resources[0].start = MX35_OTG_BASE_ADDR; |
642 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; | 406 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; |
643 | otg_resources[1].start = MXC_INT_USBOTG; | 407 | otg_resources[1].start = MXC_INT_USBOTG; |
@@ -653,6 +417,7 @@ static int __init mx3_devices_init(void) | |||
653 | imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; | 417 | imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; |
654 | imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; | 418 | imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; |
655 | } | 419 | } |
420 | #endif | ||
656 | 421 | ||
657 | return 0; | 422 | return 0; |
658 | } | 423 | } |