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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-01-06 17:33:32 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-01-06 17:33:32 -0500
commit404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34 (patch)
tree99119edc53fdca73ed7586829b8ee736e09440b3 /arch/arm/mach-mx3/devices.c
parent28cdac6690cb113856293bf79b40de33dbd8f974 (diff)
parent1051b9f0f9eab8091fe3bf98320741adf36b4cfa (diff)
Merge branch 'devel-stable' into devel
Conflicts: arch/arm/mach-pxa/clock.c arch/arm/mach-pxa/clock.h
Diffstat (limited to 'arch/arm/mach-mx3/devices.c')
-rw-r--r--arch/arm/mach-mx3/devices.c271
1 files changed, 12 insertions, 259 deletions
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index d4da9496089a..b6672db788fb 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -29,120 +29,25 @@
29 29
30#include "devices.h" 30#include "devices.h"
31 31
32/* GPIO port description */
33static struct mxc_gpio_port imx_gpio_ports[] = {
34 {
35 .chip.label = "gpio-0",
36 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
37 .irq = MXC_INT_GPIO1,
38 .virtual_irq_start = MXC_GPIO_IRQ_START,
39 }, {
40 .chip.label = "gpio-1",
41 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
42 .irq = MXC_INT_GPIO2,
43 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
44 }, {
45 .chip.label = "gpio-2",
46 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
47 .irq = MXC_INT_GPIO3,
48 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
49 }
50};
51
52int __init imx3x_register_gpios(void)
53{
54 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
55}
56
57static struct resource mxc_w1_master_resources[] = {
58 {
59 .start = OWIRE_BASE_ADDR,
60 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
61 .flags = IORESOURCE_MEM,
62 },
63};
64
65struct platform_device mxc_w1_master_device = {
66 .name = "mxc_w1",
67 .id = 0,
68 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
69 .resource = mxc_w1_master_resources,
70};
71
72#ifdef CONFIG_ARCH_MX31
73static struct resource mxcsdhc0_resources[] = {
74 {
75 .start = MX31_MMC_SDHC1_BASE_ADDR,
76 .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX31_INT_MMC_SDHC1,
80 .end = MX31_INT_MMC_SDHC1,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct resource mxcsdhc1_resources[] = {
86 {
87 .start = MX31_MMC_SDHC2_BASE_ADDR,
88 .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
89 .flags = IORESOURCE_MEM,
90 }, {
91 .start = MX31_INT_MMC_SDHC2,
92 .end = MX31_INT_MMC_SDHC2,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97struct platform_device mxcsdhc_device0 = {
98 .name = "mxc-mmc",
99 .id = 0,
100 .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
101 .resource = mxcsdhc0_resources,
102};
103
104struct platform_device mxcsdhc_device1 = {
105 .name = "mxc-mmc",
106 .id = 1,
107 .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
108 .resource = mxcsdhc1_resources,
109};
110
111static struct resource rnga_resources[] = {
112 {
113 .start = RNGA_BASE_ADDR,
114 .end = RNGA_BASE_ADDR + 0x28,
115 .flags = IORESOURCE_MEM,
116 },
117};
118
119struct platform_device mxc_rnga_device = {
120 .name = "mxc_rnga",
121 .id = -1,
122 .num_resources = 1,
123 .resource = rnga_resources,
124};
125#endif /* CONFIG_ARCH_MX31 */
126
127/* i.MX31 Image Processing Unit */ 32/* i.MX31 Image Processing Unit */
128 33
129/* The resource order is important! */ 34/* The resource order is important! */
130static struct resource mx3_ipu_rsrc[] = { 35static struct resource mx3_ipu_rsrc[] = {
131 { 36 {
132 .start = IPU_CTRL_BASE_ADDR, 37 .start = MX3x_IPU_CTRL_BASE_ADDR,
133 .end = IPU_CTRL_BASE_ADDR + 0x5F, 38 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
134 .flags = IORESOURCE_MEM, 39 .flags = IORESOURCE_MEM,
135 }, { 40 }, {
136 .start = IPU_CTRL_BASE_ADDR + 0x88, 41 .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
137 .end = IPU_CTRL_BASE_ADDR + 0xB3, 42 .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
138 .flags = IORESOURCE_MEM, 43 .flags = IORESOURCE_MEM,
139 }, { 44 }, {
140 .start = MXC_INT_IPU_SYN, 45 .start = MX3x_INT_IPU_SYN,
141 .end = MXC_INT_IPU_SYN, 46 .end = MX3x_INT_IPU_SYN,
142 .flags = IORESOURCE_IRQ, 47 .flags = IORESOURCE_IRQ,
143 }, { 48 }, {
144 .start = MXC_INT_IPU_ERR, 49 .start = MX3x_INT_IPU_ERR,
145 .end = MXC_INT_IPU_ERR, 50 .end = MX3x_INT_IPU_ERR,
146 .flags = IORESOURCE_IRQ, 51 .flags = IORESOURCE_IRQ,
147 }, 52 },
148}; 53};
@@ -156,8 +61,8 @@ struct platform_device mx3_ipu = {
156 61
157static struct resource fb_resources[] = { 62static struct resource fb_resources[] = {
158 { 63 {
159 .start = IPU_CTRL_BASE_ADDR + 0xB4, 64 .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
160 .end = IPU_CTRL_BASE_ADDR + 0x1BF, 65 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
161 .flags = IORESOURCE_MEM, 66 .flags = IORESOURCE_MEM,
162 }, 67 },
163}; 68};
@@ -174,8 +79,8 @@ struct platform_device mx3_fb = {
174 79
175static struct resource camera_resources[] = { 80static struct resource camera_resources[] = {
176 { 81 {
177 .start = IPU_CTRL_BASE_ADDR + 0x60, 82 .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
178 .end = IPU_CTRL_BASE_ADDR + 0x87, 83 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
179 .flags = IORESOURCE_MEM, 84 .flags = IORESOURCE_MEM,
180 }, 85 },
181}; 86};
@@ -190,110 +95,6 @@ struct platform_device mx3_camera = {
190 }, 95 },
191}; 96};
192 97
193static struct resource otg_resources[] = {
194 {
195 .start = MX31_OTG_BASE_ADDR,
196 .end = MX31_OTG_BASE_ADDR + 0x1ff,
197 .flags = IORESOURCE_MEM,
198 }, {
199 .start = MXC_INT_USB3,
200 .end = MXC_INT_USB3,
201 .flags = IORESOURCE_IRQ,
202 },
203};
204
205static u64 otg_dmamask = DMA_BIT_MASK(32);
206
207/* OTG gadget device */
208struct platform_device mxc_otg_udc_device = {
209 .name = "fsl-usb2-udc",
210 .id = -1,
211 .dev = {
212 .dma_mask = &otg_dmamask,
213 .coherent_dma_mask = DMA_BIT_MASK(32),
214 },
215 .resource = otg_resources,
216 .num_resources = ARRAY_SIZE(otg_resources),
217};
218
219/* OTG host */
220struct platform_device mxc_otg_host = {
221 .name = "mxc-ehci",
222 .id = 0,
223 .dev = {
224 .coherent_dma_mask = 0xffffffff,
225 .dma_mask = &otg_dmamask,
226 },
227 .resource = otg_resources,
228 .num_resources = ARRAY_SIZE(otg_resources),
229};
230
231/* USB host 1 */
232
233static u64 usbh1_dmamask = ~(u32)0;
234
235static struct resource mxc_usbh1_resources[] = {
236 {
237 .start = MX31_OTG_BASE_ADDR + 0x200,
238 .end = MX31_OTG_BASE_ADDR + 0x3ff,
239 .flags = IORESOURCE_MEM,
240 }, {
241 .start = MXC_INT_USB1,
242 .end = MXC_INT_USB1,
243 .flags = IORESOURCE_IRQ,
244 },
245};
246
247struct platform_device mxc_usbh1 = {
248 .name = "mxc-ehci",
249 .id = 1,
250 .dev = {
251 .coherent_dma_mask = 0xffffffff,
252 .dma_mask = &usbh1_dmamask,
253 },
254 .resource = mxc_usbh1_resources,
255 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
256};
257
258/* USB host 2 */
259static u64 usbh2_dmamask = ~(u32)0;
260
261static struct resource mxc_usbh2_resources[] = {
262 {
263 .start = MX31_OTG_BASE_ADDR + 0x400,
264 .end = MX31_OTG_BASE_ADDR + 0x5ff,
265 .flags = IORESOURCE_MEM,
266 }, {
267 .start = MXC_INT_USB2,
268 .end = MXC_INT_USB2,
269 .flags = IORESOURCE_IRQ,
270 },
271};
272
273struct platform_device mxc_usbh2 = {
274 .name = "mxc-ehci",
275 .id = 2,
276 .dev = {
277 .coherent_dma_mask = 0xffffffff,
278 .dma_mask = &usbh2_dmamask,
279 },
280 .resource = mxc_usbh2_resources,
281 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
282};
283
284static struct resource imx_wdt_resources[] = {
285 {
286 .flags = IORESOURCE_MEM,
287 },
288};
289
290struct platform_device imx_wdt_device0 = {
291 .name = "imx2-wdt",
292 .id = 0,
293 .num_resources = ARRAY_SIZE(imx_wdt_resources),
294 .resource = imx_wdt_resources,
295};
296
297static struct resource imx_rtc_resources[] = { 98static struct resource imx_rtc_resources[] = {
298 { 99 {
299 .start = MX31_RTC_BASE_ADDR, 100 .start = MX31_RTC_BASE_ADDR,
@@ -312,51 +113,3 @@ struct platform_device imx_rtc_device0 = {
312 .num_resources = ARRAY_SIZE(imx_rtc_resources), 113 .num_resources = ARRAY_SIZE(imx_rtc_resources),
313 .resource = imx_rtc_resources, 114 .resource = imx_rtc_resources,
314}; 115};
315
316static struct resource imx_kpp_resources[] = {
317 {
318 .start = MX3x_KPP_BASE_ADDR,
319 .end = MX3x_KPP_BASE_ADDR + 0xf,
320 .flags = IORESOURCE_MEM
321 }, {
322 .start = MX3x_INT_KPP,
323 .end = MX3x_INT_KPP,
324 .flags = IORESOURCE_IRQ,
325 },
326};
327
328struct platform_device imx_kpp_device = {
329 .name = "imx-keypad",
330 .id = -1,
331 .num_resources = ARRAY_SIZE(imx_kpp_resources),
332 .resource = imx_kpp_resources,
333};
334
335static int __init mx3_devices_init(void)
336{
337#if defined(CONFIG_ARCH_MX31)
338 if (cpu_is_mx31()) {
339 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
340 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
341 mxc_register_device(&mxc_rnga_device, NULL);
342 }
343#endif
344#if defined(CONFIG_ARCH_MX35)
345 if (cpu_is_mx35()) {
346 otg_resources[0].start = MX35_OTG_BASE_ADDR;
347 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
348 otg_resources[1].start = MXC_INT_USBOTG;
349 otg_resources[1].end = MXC_INT_USBOTG;
350 mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
351 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
352 mxc_usbh1_resources[1].start = MXC_INT_USBHS;
353 mxc_usbh1_resources[1].end = MXC_INT_USBHS;
354 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
355 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
356 }
357#endif
358
359 return 0;
360}
361
362subsys_initcall(mx3_devices_init);
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