diff options
author | Baruch Siach <baruch@tkos.co.il> | 2010-02-17 05:33:24 -0500 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-02-18 02:35:05 -0500 |
commit | 04a03e5fe3d337242e5c0a9c93d2fd24cff545ef (patch) | |
tree | 30fa99ccf96b411e5e2a4a74f237d22f86cdb4b8 /arch/arm/mach-mx25/clock.c | |
parent | f601441916d1e19291d0b4f044b4a7551e2924d0 (diff) |
mx25: add platform support for imxfb
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx25/clock.c')
-rw-r--r-- | arch/arm/mach-mx25/clock.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 744b52a613fc..56bf958d8c34 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c | |||
@@ -124,6 +124,11 @@ static unsigned long get_rate_gpt(struct clk *clk) | |||
124 | return get_rate_per(5); | 124 | return get_rate_per(5); |
125 | } | 125 | } |
126 | 126 | ||
127 | static unsigned long get_rate_lcdc(struct clk *clk) | ||
128 | { | ||
129 | return get_rate_per(7); | ||
130 | } | ||
131 | |||
127 | static unsigned long get_rate_otg(struct clk *clk) | 132 | static unsigned long get_rate_otg(struct clk *clk) |
128 | { | 133 | { |
129 | return 48000000; /* FIXME */ | 134 | return 48000000; /* FIXME */ |
@@ -167,6 +172,8 @@ DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); | |||
167 | DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); | 172 | DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); |
168 | DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); | 173 | DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); |
169 | DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); | 174 | DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); |
175 | DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); | ||
176 | DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); | ||
170 | DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); | 177 | DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); |
171 | DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); | 178 | DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); |
172 | DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); | 179 | DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); |
@@ -183,6 +190,7 @@ DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL); | |||
183 | DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); | 190 | DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); |
184 | DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); | 191 | DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); |
185 | DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); | 192 | DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); |
193 | DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); | ||
186 | 194 | ||
187 | #define _REGISTER_CLOCK(d, n, c) \ | 195 | #define _REGISTER_CLOCK(d, n, c) \ |
188 | { \ | 196 | { \ |
@@ -216,6 +224,7 @@ static struct clk_lookup lookups[] = { | |||
216 | _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) | 224 | _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) |
217 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | 225 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
218 | _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) | 226 | _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) |
227 | _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) | ||
219 | }; | 228 | }; |
220 | 229 | ||
221 | int __init mx25_clocks_init(void) | 230 | int __init mx25_clocks_init(void) |
@@ -233,6 +242,9 @@ int __init mx25_clocks_init(void) | |||
233 | __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); | 242 | __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); |
234 | __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); | 243 | __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); |
235 | 244 | ||
245 | /* Clock source for lcdc is upll */ | ||
246 | __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); | ||
247 | |||
236 | mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); | 248 | mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); |
237 | 249 | ||
238 | return 0; | 250 | return 0; |