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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-03-13 17:44:51 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-03-13 17:44:51 -0400
commit97fb44eb6bc01f4ffed4300e475aa15e44877375 (patch)
tree481ed6efd0babe7185cae04f2fd295426b36411d /arch/arm/mach-mx2/devices.c
parente4707dd3e9d0cb57597b6568a5e51fea5d6fca41 (diff)
parent148854c65ea8046b045672fd49f4333aefaa3ab5 (diff)
Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel
Conflicts: arch/arm/mach-at91/gpio.c
Diffstat (limited to 'arch/arm/mach-mx2/devices.c')
-rw-r--r--arch/arm/mach-mx2/devices.c196
1 files changed, 190 insertions, 6 deletions
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 2f9240be1c76..f81aa8a8fbb4 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -34,6 +34,10 @@
34 34
35#include <mach/irqs.h> 35#include <mach/irqs.h>
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37#include <mach/common.h>
38#include <mach/mmc.h>
39
40#include "devices.h"
37 41
38/* 42/*
39 * Resource definition for the MXC IrDA 43 * Resource definition for the MXC IrDA
@@ -225,37 +229,217 @@ struct platform_device mxc_nand_device = {
225 .resource = mxc_nand_resources, 229 .resource = mxc_nand_resources,
226}; 230};
227 231
232#ifdef CONFIG_FB_IMX
233/*
234 * lcdc:
235 * - i.MX1: the basic controller
236 * - i.MX21: to be checked
237 * - i.MX27: like i.MX1, with slightly variations
238 */
239static struct resource mxc_fb[] = {
240 {
241 .start = LCDC_BASE_ADDR,
242 .end = LCDC_BASE_ADDR + 0xFFF,
243 .flags = IORESOURCE_MEM,
244 },
245 {
246 .start = MXC_INT_LCDC,
247 .end = MXC_INT_LCDC,
248 .flags = IORESOURCE_IRQ,
249 }
250};
251
252/* mxc lcd driver */
253struct platform_device mxc_fb_device = {
254 .name = "imx-fb",
255 .id = 0,
256 .num_resources = ARRAY_SIZE(mxc_fb),
257 .resource = mxc_fb,
258 .dev = {
259 .coherent_dma_mask = 0xFFFFFFFF,
260 },
261};
262#endif
263
264#ifdef CONFIG_MACH_MX27
265static struct resource mxc_fec_resources[] = {
266 {
267 .start = FEC_BASE_ADDR,
268 .end = FEC_BASE_ADDR + 0xfff,
269 .flags = IORESOURCE_MEM
270 }, {
271 .start = MXC_INT_FEC,
272 .end = MXC_INT_FEC,
273 .flags = IORESOURCE_IRQ
274 },
275};
276
277struct platform_device mxc_fec_device = {
278 .name = "fec",
279 .id = 0,
280 .num_resources = ARRAY_SIZE(mxc_fec_resources),
281 .resource = mxc_fec_resources,
282};
283#endif
284
285static struct resource mxc_i2c_1_resources[] = {
286 [0] = {
287 .start = I2C_BASE_ADDR,
288 .end = I2C_BASE_ADDR + 0x0fff,
289 .flags = IORESOURCE_MEM
290 },
291 [1] = {
292 .start = MXC_INT_I2C,
293 .end = MXC_INT_I2C,
294 .flags = IORESOURCE_IRQ
295 }
296};
297
298struct platform_device mxc_i2c_device0 = {
299 .name = "imx-i2c",
300 .id = 0,
301 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
302 .resource = mxc_i2c_1_resources
303};
304
305#ifdef CONFIG_MACH_MX27
306static struct resource mxc_i2c_2_resources[] = {
307 [0] = {
308 .start = I2C2_BASE_ADDR,
309 .end = I2C2_BASE_ADDR + 0x0fff,
310 .flags = IORESOURCE_MEM
311 },
312 [1] = {
313 .start = MXC_INT_I2C2,
314 .end = MXC_INT_I2C2,
315 .flags = IORESOURCE_IRQ
316 }
317};
318
319struct platform_device mxc_i2c_device1 = {
320 .name = "imx-i2c",
321 .id = 1,
322 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
323 .resource = mxc_i2c_2_resources
324};
325#endif
326
327static struct resource mxc_pwm_resources[] = {
328 [0] = {
329 .start = PWM_BASE_ADDR,
330 .end = PWM_BASE_ADDR + 0x0fff,
331 .flags = IORESOURCE_MEM
332 },
333 [1] = {
334 .start = MXC_INT_PWM,
335 .end = MXC_INT_PWM,
336 .flags = IORESOURCE_IRQ,
337 }
338};
339
340struct platform_device mxc_pwm_device = {
341 .name = "mxc_pwm",
342 .id = 0,
343 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
344 .resource = mxc_pwm_resources
345};
346
347/*
348 * Resource definition for the MXC SDHC
349 */
350static struct resource mxc_sdhc1_resources[] = {
351 [0] = {
352 .start = SDHC1_BASE_ADDR,
353 .end = SDHC1_BASE_ADDR + SZ_4K - 1,
354 .flags = IORESOURCE_MEM,
355 },
356 [1] = {
357 .start = MXC_INT_SDHC1,
358 .end = MXC_INT_SDHC1,
359 .flags = IORESOURCE_IRQ,
360 },
361 [2] = {
362 .start = DMA_REQ_SDHC1,
363 .end = DMA_REQ_SDHC1,
364 .flags = IORESOURCE_DMA
365 },
366};
367
368static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
369
370struct platform_device mxc_sdhc_device0 = {
371 .name = "mxc-mmc",
372 .id = 0,
373 .dev = {
374 .dma_mask = &mxc_sdhc1_dmamask,
375 .coherent_dma_mask = 0xffffffff,
376 },
377 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
378 .resource = mxc_sdhc1_resources,
379};
380
381static struct resource mxc_sdhc2_resources[] = {
382 [0] = {
383 .start = SDHC2_BASE_ADDR,
384 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
385 .flags = IORESOURCE_MEM,
386 },
387 [1] = {
388 .start = MXC_INT_SDHC2,
389 .end = MXC_INT_SDHC2,
390 .flags = IORESOURCE_IRQ,
391 },
392 [2] = {
393 .start = DMA_REQ_SDHC2,
394 .end = DMA_REQ_SDHC2,
395 .flags = IORESOURCE_DMA
396 },
397};
398
399static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
400
401struct platform_device mxc_sdhc_device1 = {
402 .name = "mxc-mmc",
403 .id = 1,
404 .dev = {
405 .dma_mask = &mxc_sdhc2_dmamask,
406 .coherent_dma_mask = 0xffffffff,
407 },
408 .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
409 .resource = mxc_sdhc2_resources,
410};
411
228/* GPIO port description */ 412/* GPIO port description */
229static struct mxc_gpio_port imx_gpio_ports[] = { 413static struct mxc_gpio_port imx_gpio_ports[] = {
230 [0] = { 414 [0] = {
231 .chip.label = "gpio-0", 415 .chip.label = "gpio-0",
232 .irq = MXC_INT_GPIO, 416 .irq = MXC_INT_GPIO,
233 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0), 417 .base = IO_ADDRESS(GPIO_BASE_ADDR),
234 .virtual_irq_start = MXC_GPIO_IRQ_START, 418 .virtual_irq_start = MXC_GPIO_IRQ_START,
235 }, 419 },
236 [1] = { 420 [1] = {
237 .chip.label = "gpio-1", 421 .chip.label = "gpio-1",
238 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1), 422 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
239 .virtual_irq_start = MXC_GPIO_IRQ_START + 32, 423 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
240 }, 424 },
241 [2] = { 425 [2] = {
242 .chip.label = "gpio-2", 426 .chip.label = "gpio-2",
243 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2), 427 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
244 .virtual_irq_start = MXC_GPIO_IRQ_START + 64, 428 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
245 }, 429 },
246 [3] = { 430 [3] = {
247 .chip.label = "gpio-3", 431 .chip.label = "gpio-3",
248 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3), 432 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
249 .virtual_irq_start = MXC_GPIO_IRQ_START + 96, 433 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
250 }, 434 },
251 [4] = { 435 [4] = {
252 .chip.label = "gpio-4", 436 .chip.label = "gpio-4",
253 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4), 437 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
254 .virtual_irq_start = MXC_GPIO_IRQ_START + 128, 438 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
255 }, 439 },
256 [5] = { 440 [5] = {
257 .chip.label = "gpio-5", 441 .chip.label = "gpio-5",
258 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5), 442 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
259 .virtual_irq_start = MXC_GPIO_IRQ_START + 160, 443 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
260 } 444 }
261}; 445};