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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-06-14 09:56:58 -0400
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-06-30 02:59:44 -0400
commit074694956b547de9a6b85b919c0bb13853b88c2d (patch)
tree3abf7837bdb3c03a76f0d4d8b41a6bb1b06797e2 /arch/arm/mach-mx1
parent551823e7e031978b990e952c70ae01f8eba8d2c4 (diff)
ARM: imx: move mx1 support to mach-imx
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx1')
-rw-r--r--arch/arm/mach-mx1/Kconfig19
-rw-r--r--arch/arm/mach-mx1/Makefile14
-rw-r--r--arch/arm/mach-mx1/Makefile.boot4
-rw-r--r--arch/arm/mach-mx1/clock.c636
-rw-r--r--arch/arm/mach-mx1/devices.c220
-rw-r--r--arch/arm/mach-mx1/devices.h7
-rw-r--r--arch/arm/mach-mx1/generic.c55
-rw-r--r--arch/arm/mach-mx1/ksym_mx1.c18
-rw-r--r--arch/arm/mach-mx1/mach-mx1ads.c165
-rw-r--r--arch/arm/mach-mx1/mach-scb9328.c157
-rw-r--r--arch/arm/mach-mx1/mx1_camera_fiq.S35
11 files changed, 0 insertions, 1330 deletions
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig
deleted file mode 100644
index eb7660f5d4b7..000000000000
--- a/arch/arm/mach-mx1/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
1if ARCH_MX1
2
3comment "MX1 platforms:"
4
5config MACH_MXLADS
6 bool
7
8config ARCH_MX1ADS
9 bool "MX1ADS platform"
10 select MACH_MXLADS
11 help
12 Say Y here if you are using Motorola MX1ADS/MXLADS boards
13
14config MACH_SCB9328
15 bool "Synertronixx scb9328"
16 help
17 Say Y here if you are using a Synertronixx scb9328 board
18
19endif
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
deleted file mode 100644
index 297d17210e11..000000000000
--- a/arch/arm/mach-mx1/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y += generic.o clock.o devices.o
8
9# Support for CMOS sensor interface
10obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o
11
12# Specific board support
13obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
14obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot
deleted file mode 100644
index 8ed1492288a2..000000000000
--- a/arch/arm/mach-mx1/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
1 zreladdr-y := 0x08008000
2params_phys-y := 0x08000100
3initrd_phys-y := 0x08800000
4
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
deleted file mode 100644
index c05096c38301..000000000000
--- a/arch/arm/mach-mx1/clock.c
+++ /dev/null
@@ -1,636 +0,0 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/list.h>
21#include <linux/math64.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include <asm/clkdev.h>
27
28#include <mach/clock.h>
29#include <mach/hardware.h>
30#include <mach/common.h>
31
32#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
33
34/* CCM register addresses */
35#define CCM_CSCR IO_ADDR_CCM(0x0)
36#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
37#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
38#define CCM_PCDR IO_ADDR_CCM(0x20)
39
40#define CCM_CSCR_CLKO_OFFSET 29
41#define CCM_CSCR_CLKO_MASK (0x7 << 29)
42#define CCM_CSCR_USB_OFFSET 26
43#define CCM_CSCR_USB_MASK (0x7 << 26)
44#define CCM_CSCR_OSC_EN_SHIFT 17
45#define CCM_CSCR_SYSTEM_SEL (1 << 16)
46#define CCM_CSCR_BCLK_OFFSET 10
47#define CCM_CSCR_BCLK_MASK (0xf << 10)
48#define CCM_CSCR_PRESC (1 << 15)
49
50#define CCM_PCDR_PCLK3_OFFSET 16
51#define CCM_PCDR_PCLK3_MASK (0x7f << 16)
52#define CCM_PCDR_PCLK2_OFFSET 4
53#define CCM_PCDR_PCLK2_MASK (0xf << 4)
54#define CCM_PCDR_PCLK1_OFFSET 0
55#define CCM_PCDR_PCLK1_MASK 0xf
56
57#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
58
59/* SCM register addresses */
60#define SCM_GCCR IO_ADDR_SCM(0xc)
61
62#define SCM_GCCR_DMA_CLK_EN_OFFSET 3
63#define SCM_GCCR_CSI_CLK_EN_OFFSET 2
64#define SCM_GCCR_MMA_CLK_EN_OFFSET 1
65#define SCM_GCCR_USBD_CLK_EN_OFFSET 0
66
67static int _clk_enable(struct clk *clk)
68{
69 unsigned int reg;
70
71 reg = __raw_readl(clk->enable_reg);
72 reg |= 1 << clk->enable_shift;
73 __raw_writel(reg, clk->enable_reg);
74
75 return 0;
76}
77
78static void _clk_disable(struct clk *clk)
79{
80 unsigned int reg;
81
82 reg = __raw_readl(clk->enable_reg);
83 reg &= ~(1 << clk->enable_shift);
84 __raw_writel(reg, clk->enable_reg);
85}
86
87static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
88 struct clk *parent)
89{
90 int i;
91
92 for (i = 0; i < size; i++)
93 if (parent == clk_arr[i])
94 return i;
95
96 return -EINVAL;
97}
98
99static unsigned long
100_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
101{
102 int div;
103 unsigned long parent_rate;
104
105 parent_rate = clk_get_rate(clk->parent);
106
107 div = parent_rate / rate;
108 if (parent_rate % rate)
109 div++;
110
111 if (div > limit)
112 div = limit;
113
114 return parent_rate / div;
115}
116
117static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
118{
119 return clk->parent->round_rate(clk->parent, rate);
120}
121
122static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
123{
124 return clk->parent->set_rate(clk->parent, rate);
125}
126
127static unsigned long clk16m_get_rate(struct clk *clk)
128{
129 return 16000000;
130}
131
132static struct clk clk16m = {
133 .get_rate = clk16m_get_rate,
134 .enable = _clk_enable,
135 .enable_reg = CCM_CSCR,
136 .enable_shift = CCM_CSCR_OSC_EN_SHIFT,
137 .disable = _clk_disable,
138};
139
140/* in Hz */
141static unsigned long clk32_rate;
142
143static unsigned long clk32_get_rate(struct clk *clk)
144{
145 return clk32_rate;
146}
147
148static struct clk clk32 = {
149 .get_rate = clk32_get_rate,
150};
151
152static unsigned long clk32_premult_get_rate(struct clk *clk)
153{
154 return clk_get_rate(clk->parent) * 512;
155}
156
157static struct clk clk32_premult = {
158 .parent = &clk32,
159 .get_rate = clk32_premult_get_rate,
160};
161
162static const struct clk *prem_clk_clocks[] = {
163 &clk32_premult,
164 &clk16m,
165};
166
167static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
168{
169 int i;
170 unsigned int reg = __raw_readl(CCM_CSCR);
171
172 i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
173 parent);
174
175 switch (i) {
176 case 0:
177 reg &= ~CCM_CSCR_SYSTEM_SEL;
178 break;
179 case 1:
180 reg |= CCM_CSCR_SYSTEM_SEL;
181 break;
182 default:
183 return i;
184 }
185
186 __raw_writel(reg, CCM_CSCR);
187
188 return 0;
189}
190
191static struct clk prem_clk = {
192 .set_parent = prem_clk_set_parent,
193};
194
195static unsigned long system_clk_get_rate(struct clk *clk)
196{
197 return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
198 clk_get_rate(clk->parent));
199}
200
201static struct clk system_clk = {
202 .parent = &prem_clk,
203 .get_rate = system_clk_get_rate,
204};
205
206static unsigned long mcu_clk_get_rate(struct clk *clk)
207{
208 return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
209 clk_get_rate(clk->parent));
210}
211
212static struct clk mcu_clk = {
213 .parent = &clk32_premult,
214 .get_rate = mcu_clk_get_rate,
215};
216
217static unsigned long fclk_get_rate(struct clk *clk)
218{
219 unsigned long fclk = clk_get_rate(clk->parent);
220
221 if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
222 fclk /= 2;
223
224 return fclk;
225}
226
227static struct clk fclk = {
228 .parent = &mcu_clk,
229 .get_rate = fclk_get_rate,
230};
231
232/*
233 * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
234 */
235static unsigned long hclk_get_rate(struct clk *clk)
236{
237 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
238 CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
239}
240
241static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
242{
243 return _clk_simple_round_rate(clk, rate, 16);
244}
245
246static int hclk_set_rate(struct clk *clk, unsigned long rate)
247{
248 unsigned int div;
249 unsigned int reg;
250 unsigned long parent_rate;
251
252 parent_rate = clk_get_rate(clk->parent);
253
254 div = parent_rate / rate;
255
256 if (div > 16 || div < 1 || ((parent_rate / div) != rate))
257 return -EINVAL;
258
259 div--;
260
261 reg = __raw_readl(CCM_CSCR);
262 reg &= ~CCM_CSCR_BCLK_MASK;
263 reg |= div << CCM_CSCR_BCLK_OFFSET;
264 __raw_writel(reg, CCM_CSCR);
265
266 return 0;
267}
268
269static struct clk hclk = {
270 .parent = &system_clk,
271 .get_rate = hclk_get_rate,
272 .round_rate = hclk_round_rate,
273 .set_rate = hclk_set_rate,
274};
275
276static unsigned long clk48m_get_rate(struct clk *clk)
277{
278 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
279 CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
280}
281
282static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
283{
284 return _clk_simple_round_rate(clk, rate, 8);
285}
286
287static int clk48m_set_rate(struct clk *clk, unsigned long rate)
288{
289 unsigned int div;
290 unsigned int reg;
291 unsigned long parent_rate;
292
293 parent_rate = clk_get_rate(clk->parent);
294
295 div = parent_rate / rate;
296
297 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
298 return -EINVAL;
299
300 div--;
301
302 reg = __raw_readl(CCM_CSCR);
303 reg &= ~CCM_CSCR_USB_MASK;
304 reg |= div << CCM_CSCR_USB_OFFSET;
305 __raw_writel(reg, CCM_CSCR);
306
307 return 0;
308}
309
310static struct clk clk48m = {
311 .parent = &system_clk,
312 .get_rate = clk48m_get_rate,
313 .round_rate = clk48m_round_rate,
314 .set_rate = clk48m_set_rate,
315};
316
317/*
318 * get peripheral clock 1 ( UART[12], Timer[12], PWM )
319 */
320static unsigned long perclk1_get_rate(struct clk *clk)
321{
322 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
323 CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
324}
325
326static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
327{
328 return _clk_simple_round_rate(clk, rate, 16);
329}
330
331static int perclk1_set_rate(struct clk *clk, unsigned long rate)
332{
333 unsigned int div;
334 unsigned int reg;
335 unsigned long parent_rate;
336
337 parent_rate = clk_get_rate(clk->parent);
338
339 div = parent_rate / rate;
340
341 if (div > 16 || div < 1 || ((parent_rate / div) != rate))
342 return -EINVAL;
343
344 div--;
345
346 reg = __raw_readl(CCM_PCDR);
347 reg &= ~CCM_PCDR_PCLK1_MASK;
348 reg |= div << CCM_PCDR_PCLK1_OFFSET;
349 __raw_writel(reg, CCM_PCDR);
350
351 return 0;
352}
353
354/*
355 * get peripheral clock 2 ( LCD, SD, SPI[12] )
356 */
357static unsigned long perclk2_get_rate(struct clk *clk)
358{
359 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
360 CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
361}
362
363static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
364{
365 return _clk_simple_round_rate(clk, rate, 16);
366}
367
368static int perclk2_set_rate(struct clk *clk, unsigned long rate)
369{
370 unsigned int div;
371 unsigned int reg;
372 unsigned long parent_rate;
373
374 parent_rate = clk_get_rate(clk->parent);
375
376 div = parent_rate / rate;
377
378 if (div > 16 || div < 1 || ((parent_rate / div) != rate))
379 return -EINVAL;
380
381 div--;
382
383 reg = __raw_readl(CCM_PCDR);
384 reg &= ~CCM_PCDR_PCLK2_MASK;
385 reg |= div << CCM_PCDR_PCLK2_OFFSET;
386 __raw_writel(reg, CCM_PCDR);
387
388 return 0;
389}
390
391/*
392 * get peripheral clock 3 ( SSI )
393 */
394static unsigned long perclk3_get_rate(struct clk *clk)
395{
396 return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
397 CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
398}
399
400static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
401{
402 return _clk_simple_round_rate(clk, rate, 128);
403}
404
405static int perclk3_set_rate(struct clk *clk, unsigned long rate)
406{
407 unsigned int div;
408 unsigned int reg;
409 unsigned long parent_rate;
410
411 parent_rate = clk_get_rate(clk->parent);
412
413 div = parent_rate / rate;
414
415 if (div > 128 || div < 1 || ((parent_rate / div) != rate))
416 return -EINVAL;
417
418 div--;
419
420 reg = __raw_readl(CCM_PCDR);
421 reg &= ~CCM_PCDR_PCLK3_MASK;
422 reg |= div << CCM_PCDR_PCLK3_OFFSET;
423 __raw_writel(reg, CCM_PCDR);
424
425 return 0;
426}
427
428static struct clk perclk[] = {
429 {
430 .id = 0,
431 .parent = &system_clk,
432 .get_rate = perclk1_get_rate,
433 .round_rate = perclk1_round_rate,
434 .set_rate = perclk1_set_rate,
435 }, {
436 .id = 1,
437 .parent = &system_clk,
438 .get_rate = perclk2_get_rate,
439 .round_rate = perclk2_round_rate,
440 .set_rate = perclk2_set_rate,
441 }, {
442 .id = 2,
443 .parent = &system_clk,
444 .get_rate = perclk3_get_rate,
445 .round_rate = perclk3_round_rate,
446 .set_rate = perclk3_set_rate,
447 }
448};
449
450static const struct clk *clko_clocks[] = {
451 &perclk[0],
452 &hclk,
453 &clk48m,
454 &clk16m,
455 &prem_clk,
456 &fclk,
457};
458
459static int clko_set_parent(struct clk *clk, struct clk *parent)
460{
461 int i;
462 unsigned int reg;
463
464 i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
465 if (i < 0)
466 return i;
467
468 reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
469 reg |= i << CCM_CSCR_CLKO_OFFSET;
470 __raw_writel(reg, CCM_CSCR);
471
472 if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
473 clk->set_rate = _clk_parent_set_rate;
474 clk->round_rate = _clk_parent_round_rate;
475 } else {
476 clk->set_rate = NULL;
477 clk->round_rate = NULL;
478 }
479
480 return 0;
481}
482
483static struct clk clko_clk = {
484 .set_parent = clko_set_parent,
485};
486
487static struct clk dma_clk = {
488 .parent = &hclk,
489 .round_rate = _clk_parent_round_rate,
490 .set_rate = _clk_parent_set_rate,
491 .enable = _clk_enable,
492 .enable_reg = SCM_GCCR,
493 .enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
494 .disable = _clk_disable,
495};
496
497static struct clk csi_clk = {
498 .parent = &hclk,
499 .round_rate = _clk_parent_round_rate,
500 .set_rate = _clk_parent_set_rate,
501 .enable = _clk_enable,
502 .enable_reg = SCM_GCCR,
503 .enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
504 .disable = _clk_disable,
505};
506
507static struct clk mma_clk = {
508 .parent = &hclk,
509 .round_rate = _clk_parent_round_rate,
510 .set_rate = _clk_parent_set_rate,
511 .enable = _clk_enable,
512 .enable_reg = SCM_GCCR,
513 .enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
514 .disable = _clk_disable,
515};
516
517static struct clk usbd_clk = {
518 .parent = &clk48m,
519 .round_rate = _clk_parent_round_rate,
520 .set_rate = _clk_parent_set_rate,
521 .enable = _clk_enable,
522 .enable_reg = SCM_GCCR,
523 .enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
524 .disable = _clk_disable,
525};
526
527static struct clk gpt_clk = {
528 .parent = &perclk[0],
529 .round_rate = _clk_parent_round_rate,
530 .set_rate = _clk_parent_set_rate,
531};
532
533static struct clk uart_clk = {
534 .parent = &perclk[0],
535 .round_rate = _clk_parent_round_rate,
536 .set_rate = _clk_parent_set_rate,
537};
538
539static struct clk i2c_clk = {
540 .parent = &hclk,
541 .round_rate = _clk_parent_round_rate,
542 .set_rate = _clk_parent_set_rate,
543};
544
545static struct clk spi_clk = {
546 .parent = &perclk[1],
547 .round_rate = _clk_parent_round_rate,
548 .set_rate = _clk_parent_set_rate,
549};
550
551static struct clk sdhc_clk = {
552 .parent = &perclk[1],
553 .round_rate = _clk_parent_round_rate,
554 .set_rate = _clk_parent_set_rate,
555};
556
557static struct clk lcdc_clk = {
558 .parent = &perclk[1],
559 .round_rate = _clk_parent_round_rate,
560 .set_rate = _clk_parent_set_rate,
561};
562
563static struct clk mshc_clk = {
564 .parent = &hclk,
565 .round_rate = _clk_parent_round_rate,
566 .set_rate = _clk_parent_set_rate,
567};
568
569static struct clk ssi_clk = {
570 .parent = &perclk[2],
571 .round_rate = _clk_parent_round_rate,
572 .set_rate = _clk_parent_set_rate,
573};
574
575static struct clk rtc_clk = {
576 .parent = &clk32,
577};
578
579#define _REGISTER_CLOCK(d, n, c) \
580 { \
581 .dev_id = d, \
582 .con_id = n, \
583 .clk = &c, \
584 },
585static struct clk_lookup lookups[] __initdata = {
586 _REGISTER_CLOCK(NULL, "dma", dma_clk)
587 _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
588 _REGISTER_CLOCK(NULL, "mma", mma_clk)
589 _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
590 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
591 _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
592 _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
593 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
594 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
595 _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
596 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
597 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
598 _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
599 _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
600 _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
601};
602
603int __init mx1_clocks_init(unsigned long fref)
604{
605 unsigned int reg;
606
607 /* disable clocks we are able to */
608 __raw_writel(0, SCM_GCCR);
609
610 clk32_rate = fref;
611 reg = __raw_readl(CCM_CSCR);
612
613 /* detect clock reference for system PLL */
614 if (reg & CCM_CSCR_SYSTEM_SEL) {
615 prem_clk.parent = &clk16m;
616 } else {
617 /* ensure that oscillator is disabled */
618 reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
619 __raw_writel(reg, CCM_CSCR);
620 prem_clk.parent = &clk32_premult;
621 }
622
623 /* detect reference for CLKO */
624 reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
625 clko_clk.parent = (struct clk *)clko_clocks[reg];
626
627 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
628
629 clk_enable(&hclk);
630 clk_enable(&fclk);
631
632 mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
633 MX1_TIM1_INT);
634
635 return 0;
636}
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
deleted file mode 100644
index a79e6132dbe5..000000000000
--- a/arch/arm/mach-mx1/devices.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
19 * Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/gpio.h>
27#include <mach/irqs.h>
28#include <mach/hardware.h>
29
30#include "devices.h"
31
32static struct resource imx1_camera_resources[] = {
33 {
34 .start = 0x00224000,
35 .end = 0x00224010,
36 .flags = IORESOURCE_MEM,
37 }, {
38 .start = MX1_CSI_INT,
39 .end = MX1_CSI_INT,
40 .flags = IORESOURCE_IRQ,
41 },
42};
43
44static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
45
46struct platform_device imx1_camera_device = {
47 .name = "mx1-camera",
48 .id = 0, /* This is used to put cameras on this interface */
49 .dev = {
50 .dma_mask = &imx1_camera_dmamask,
51 .coherent_dma_mask = DMA_BIT_MASK(32),
52 },
53 .resource = imx1_camera_resources,
54 .num_resources = ARRAY_SIZE(imx1_camera_resources),
55};
56
57static struct resource imx_i2c_resources[] = {
58 {
59 .start = 0x00217000,
60 .end = 0x00217010,
61 .flags = IORESOURCE_MEM,
62 }, {
63 .start = MX1_I2C_INT,
64 .end = MX1_I2C_INT,
65 .flags = IORESOURCE_IRQ,
66 },
67};
68
69struct platform_device imx_i2c_device0 = {
70 .name = "imx-i2c",
71 .id = 0,
72 .resource = imx_i2c_resources,
73 .num_resources = ARRAY_SIZE(imx_i2c_resources),
74};
75
76#define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts) \
77 static struct resource imx1_uart_resources ## n[] = { \
78 { \
79 .start = baseaddr, \
80 .end = baseaddr + 0xd0, \
81 .flags = IORESOURCE_MEM, \
82 }, { \
83 .start = irqrx, \
84 .end = irqrx, \
85 .flags = IORESOURCE_IRQ, \
86 }, { \
87 .start = irqtx, \
88 .end = irqtx, \
89 .flags = IORESOURCE_IRQ, \
90 }, { \
91 .start = irqrts, \
92 .end = irqrts, \
93 .flags = IORESOURCE_IRQ, \
94 }, \
95 }; \
96 \
97 struct platform_device imx1_uart_device ## n = { \
98 .name = "imx-uart", \
99 .id = n, \
100 .num_resources = ARRAY_SIZE(imx1_uart_resources ## n), \
101 .resource = imx1_uart_resources ## n, \
102 }
103
104DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS);
105DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS);
106
107static struct resource imx_rtc_resources[] = {
108 {
109 .start = 0x00204000,
110 .end = 0x00204024,
111 .flags = IORESOURCE_MEM,
112 }, {
113 .start = MX1_RTC_INT,
114 .end = MX1_RTC_INT,
115 .flags = IORESOURCE_IRQ,
116 }, {
117 .start = MX1_RTC_SAMINT,
118 .end = MX1_RTC_SAMINT,
119 .flags = IORESOURCE_IRQ,
120 },
121};
122
123struct platform_device imx_rtc_device = {
124 .name = "rtc-imx",
125 .id = 0,
126 .resource = imx_rtc_resources,
127 .num_resources = ARRAY_SIZE(imx_rtc_resources),
128};
129
130static struct resource imx_wdt_resources[] = {
131 {
132 .start = 0x00201000,
133 .end = 0x00201008,
134 .flags = IORESOURCE_MEM,
135 }, {
136 .start = MX1_WDT_INT,
137 .end = MX1_WDT_INT,
138 .flags = IORESOURCE_IRQ,
139 },
140};
141
142struct platform_device imx_wdt_device = {
143 .name = "imx-wdt",
144 .id = 0,
145 .resource = imx_wdt_resources,
146 .num_resources = ARRAY_SIZE(imx_wdt_resources),
147};
148
149static struct resource imx_usb_resources[] = {
150 {
151 .start = 0x00212000,
152 .end = 0x00212148,
153 .flags = IORESOURCE_MEM,
154 }, {
155 .start = MX1_USBD_INT0,
156 .end = MX1_USBD_INT0,
157 .flags = IORESOURCE_IRQ,
158 }, {
159 .start = MX1_USBD_INT1,
160 .end = MX1_USBD_INT1,
161 .flags = IORESOURCE_IRQ,
162 }, {
163 .start = MX1_USBD_INT2,
164 .end = MX1_USBD_INT2,
165 .flags = IORESOURCE_IRQ,
166 }, {
167 .start = MX1_USBD_INT3,
168 .end = MX1_USBD_INT3,
169 .flags = IORESOURCE_IRQ,
170 }, {
171 .start = MX1_USBD_INT4,
172 .end = MX1_USBD_INT4,
173 .flags = IORESOURCE_IRQ,
174 }, {
175 .start = MX1_USBD_INT5,
176 .end = MX1_USBD_INT5,
177 .flags = IORESOURCE_IRQ,
178 }, {
179 .start = MX1_USBD_INT6,
180 .end = MX1_USBD_INT6,
181 .flags = IORESOURCE_IRQ,
182 },
183};
184
185struct platform_device imx_usb_device = {
186 .name = "imx_udc",
187 .id = 0,
188 .num_resources = ARRAY_SIZE(imx_usb_resources),
189 .resource = imx_usb_resources,
190};
191
192/* GPIO port description */
193static struct mxc_gpio_port imx_gpio_ports[] = {
194 {
195 .chip.label = "gpio-0",
196 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
197 .irq = MX1_GPIO_INT_PORTA,
198 .virtual_irq_start = MXC_GPIO_IRQ_START,
199 }, {
200 .chip.label = "gpio-1",
201 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
202 .irq = MX1_GPIO_INT_PORTB,
203 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
204 }, {
205 .chip.label = "gpio-2",
206 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
207 .irq = MX1_GPIO_INT_PORTC,
208 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
209 }, {
210 .chip.label = "gpio-3",
211 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
212 .irq = MX1_GPIO_INT_PORTD,
213 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
214 }
215};
216
217int __init imx1_register_gpios(void)
218{
219 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
220}
diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
deleted file mode 100644
index 13325166f639..000000000000
--- a/arch/arm/mach-mx1/devices.h
+++ /dev/null
@@ -1,7 +0,0 @@
1extern struct platform_device imx1_camera_device;
2extern struct platform_device imx_i2c_device0;
3extern struct platform_device imx1_uart_device0;
4extern struct platform_device imx1_uart_device1;
5extern struct platform_device imx_rtc_device;
6extern struct platform_device imx_wdt_device;
7extern struct platform_device imx_usb_device;
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
deleted file mode 100644
index a9be5f14bd9d..000000000000
--- a/arch/arm/mach-mx1/generic.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * author: Sascha Hauer
3 * Created: april 20th, 2004
4 * Copyright: Synertronixx GmbH
5 *
6 * Common code for i.MX machines
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/io.h>
26
27#include <asm/mach/map.h>
28
29#include <mach/common.h>
30#include <mach/hardware.h>
31
32static struct map_desc imx_io_desc[] __initdata = {
33 {
34 .virtual = MX1_IO_BASE_ADDR_VIRT,
35 .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
36 .length = MX1_IO_SIZE,
37 .type = MT_DEVICE
38 }
39};
40
41void __init mx1_map_io(void)
42{
43 mxc_set_cpu_type(MXC_CPU_MX1);
44 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
45
46 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
47}
48
49int imx1_register_gpios(void);
50
51void __init mx1_init_irq(void)
52{
53 imx1_register_gpios();
54 mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
55}
diff --git a/arch/arm/mach-mx1/ksym_mx1.c b/arch/arm/mach-mx1/ksym_mx1.c
deleted file mode 100644
index b09ee12a4ff0..000000000000
--- a/arch/arm/mach-mx1/ksym_mx1.c
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Exported ksyms of ARCH_MX1
3 *
4 * Copyright (C) 2008, Darius Augulis <augulis.darius@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/module.h>
13
14#include <mach/mx1_camera.h>
15
16/* IMX camera FIQ handler */
17EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
18EXPORT_SYMBOL(mx1_camera_sof_fiq_end);
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c
deleted file mode 100644
index 5d7c85f8aaf5..000000000000
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ /dev/null
@@ -1,165 +0,0 @@
1/*
2 * arch/arm/mach-imx/mach-mx1ads.c
3 *
4 * Initially based on:
5 * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
6 * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
7 *
8 * 2004 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/i2c.h>
16#include <linux/i2c/pcf857x.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/mtd/physmap.h>
21
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/time.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/i2c.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux-mx1.h>
31#include <mach/irqs.h>
32
33#include "devices.h"
34
35static int mx1ads_pins[] = {
36 /* UART1 */
37 PC9_PF_UART1_CTS,
38 PC10_PF_UART1_RTS,
39 PC11_PF_UART1_TXD,
40 PC12_PF_UART1_RXD,
41 /* UART2 */
42 PB28_PF_UART2_CTS,
43 PB29_PF_UART2_RTS,
44 PB30_PF_UART2_TXD,
45 PB31_PF_UART2_RXD,
46 /* I2C */
47 PA15_PF_I2C_SDA,
48 PA16_PF_I2C_SCL,
49 /* SPI */
50 PC13_PF_SPI1_SPI_RDY,
51 PC14_PF_SPI1_SCLK,
52 PC15_PF_SPI1_SS,
53 PC16_PF_SPI1_MISO,
54 PC17_PF_SPI1_MOSI,
55};
56
57/*
58 * UARTs platform data
59 */
60
61static struct imxuart_platform_data uart_pdata[] = {
62 {
63 .flags = IMXUART_HAVE_RTSCTS,
64 }, {
65 .flags = IMXUART_HAVE_RTSCTS,
66 },
67};
68
69/*
70 * Physmap flash
71 */
72
73static struct physmap_flash_data mx1ads_flash_data = {
74 .width = 4, /* bankwidth in bytes */
75};
76
77static struct resource flash_resource = {
78 .start = MX1_CS0_PHYS,
79 .end = MX1_CS0_PHYS + SZ_32M - 1,
80 .flags = IORESOURCE_MEM,
81};
82
83static struct platform_device flash_device = {
84 .name = "physmap-flash",
85 .id = 0,
86 .resource = &flash_resource,
87 .num_resources = 1,
88};
89
90/*
91 * I2C
92 */
93static struct pcf857x_platform_data pcf857x_data[] = {
94 {
95 .gpio_base = 4 * 32,
96 }, {
97 .gpio_base = 4 * 32 + 16,
98 }
99};
100
101static struct imxi2c_platform_data mx1ads_i2c_data = {
102 .bitrate = 100000,
103};
104
105static struct i2c_board_info mx1ads_i2c_devices[] = {
106 {
107 I2C_BOARD_INFO("pcf8575", 0x22),
108 .platform_data = &pcf857x_data[0],
109 }, {
110 I2C_BOARD_INFO("pcf8575", 0x24),
111 .platform_data = &pcf857x_data[1],
112 },
113};
114
115/*
116 * Board init
117 */
118static void __init mx1ads_init(void)
119{
120 mxc_gpio_setup_multiple_pins(mx1ads_pins,
121 ARRAY_SIZE(mx1ads_pins), "mx1ads");
122
123 /* UART */
124 mxc_register_device(&imx1_uart_device0, &uart_pdata[0]);
125 mxc_register_device(&imx1_uart_device1, &uart_pdata[1]);
126
127 /* Physmap flash */
128 mxc_register_device(&flash_device, &mx1ads_flash_data);
129
130 /* I2C */
131 i2c_register_board_info(0, mx1ads_i2c_devices,
132 ARRAY_SIZE(mx1ads_i2c_devices));
133
134 mxc_register_device(&imx_i2c_device0, &mx1ads_i2c_data);
135}
136
137static void __init mx1ads_timer_init(void)
138{
139 mx1_clocks_init(32000);
140}
141
142struct sys_timer mx1ads_timer = {
143 .init = mx1ads_timer_init,
144};
145
146MACHINE_START(MX1ADS, "Freescale MX1ADS")
147 /* Maintainer: Sascha Hauer, Pengutronix */
148 .phys_io = MX1_IO_BASE_ADDR,
149 .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
150 .boot_params = MX1_PHYS_OFFSET + 0x100,
151 .map_io = mx1_map_io,
152 .init_irq = mx1_init_irq,
153 .timer = &mx1ads_timer,
154 .init_machine = mx1ads_init,
155MACHINE_END
156
157MACHINE_START(MXLADS, "Freescale MXLADS")
158 .phys_io = MX1_IO_BASE_ADDR,
159 .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
160 .boot_params = MX1_PHYS_OFFSET + 0x100,
161 .map_io = mx1_map_io,
162 .init_irq = mx1_init_irq,
163 .timer = &mx1ads_timer,
164 .init_machine = mx1ads_init,
165MACHINE_END
diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c
deleted file mode 100644
index 482b24df4624..000000000000
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * linux/arch/arm/mach-mx1/mach-scb9328.c
3 *
4 * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
5 * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#include <linux/platform_device.h>
14#include <linux/mtd/physmap.h>
15#include <linux/interrupt.h>
16#include <linux/dm9000.h>
17
18#include <asm/mach-types.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/time.h>
21
22#include <mach/common.h>
23#include <mach/hardware.h>
24#include <mach/irqs.h>
25#include <mach/imx-uart.h>
26#include <mach/iomux-mx1.h>
27
28#include "devices.h"
29
30/*
31 * This scb9328 has a 32MiB flash
32 */
33static struct resource flash_resource = {
34 .start = MX1_CS0_PHYS,
35 .end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
36 .flags = IORESOURCE_MEM,
37};
38
39static struct physmap_flash_data scb_flash_data = {
40 .width = 2,
41};
42
43static struct platform_device scb_flash_device = {
44 .name = "physmap-flash",
45 .id = 0,
46 .dev = {
47 .platform_data = &scb_flash_data,
48 },
49 .resource = &flash_resource,
50 .num_resources = 1,
51};
52
53/*
54 * scb9328 has a DM9000 network controller
55 * connected to CS5, with 16 bit data path
56 * and interrupt connected to GPIO 3
57 */
58
59/*
60 * internal datapath is fixed 16 bit
61 */
62static struct dm9000_plat_data dm9000_platdata = {
63 .flags = DM9000_PLATF_16BITONLY,
64};
65
66/*
67 * the DM9000 drivers wants two defined address spaces
68 * to gain access to address latch registers and the data path.
69 */
70static struct resource dm9000x_resources[] = {
71 {
72 .name = "address area",
73 .start = MX1_CS5_PHYS,
74 .end = MX1_CS5_PHYS + 1,
75 .flags = IORESOURCE_MEM, /* address access */
76 }, {
77 .name = "data area",
78 .start = MX1_CS5_PHYS + 4,
79 .end = MX1_CS5_PHYS + 5,
80 .flags = IORESOURCE_MEM, /* data access */
81 }, {
82 .start = IRQ_GPIOC(3),
83 .end = IRQ_GPIOC(3),
84 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
85 },
86};
87
88static struct platform_device dm9000x_device = {
89 .name = "dm9000",
90 .id = 0,
91 .num_resources = ARRAY_SIZE(dm9000x_resources),
92 .resource = dm9000x_resources,
93 .dev = {
94 .platform_data = &dm9000_platdata,
95 }
96};
97
98static int mxc_uart1_pins[] = {
99 PC9_PF_UART1_CTS,
100 PC10_PF_UART1_RTS,
101 PC11_PF_UART1_TXD,
102 PC12_PF_UART1_RXD,
103};
104
105static int uart1_mxc_init(struct platform_device *pdev)
106{
107 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
108 ARRAY_SIZE(mxc_uart1_pins), "UART1");
109}
110
111static void uart1_mxc_exit(struct platform_device *pdev)
112{
113 mxc_gpio_release_multiple_pins(mxc_uart1_pins,
114 ARRAY_SIZE(mxc_uart1_pins));
115}
116
117static struct imxuart_platform_data uart_pdata = {
118 .init = uart1_mxc_init,
119 .exit = uart1_mxc_exit,
120 .flags = IMXUART_HAVE_RTSCTS,
121};
122
123static struct platform_device *devices[] __initdata = {
124 &scb_flash_device,
125 &dm9000x_device,
126};
127
128/*
129 * scb9328_init - Init the CPU card itself
130 */
131static void __init scb9328_init(void)
132{
133 mxc_register_device(&imx1_uart_device0, &uart_pdata);
134
135 printk(KERN_INFO"Scb9328: Adding devices\n");
136 platform_add_devices(devices, ARRAY_SIZE(devices));
137}
138
139static void __init scb9328_timer_init(void)
140{
141 mx1_clocks_init(32000);
142}
143
144static struct sys_timer scb9328_timer = {
145 .init = scb9328_timer_init,
146};
147
148MACHINE_START(SCB9328, "Synertronixx scb9328")
149 /* Sascha Hauer */
150 .phys_io = 0x00200000,
151 .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc,
152 .boot_params = 0x08000100,
153 .map_io = mx1_map_io,
154 .init_irq = mx1_init_irq,
155 .timer = &scb9328_timer,
156 .init_machine = scb9328_init,
157MACHINE_END
diff --git a/arch/arm/mach-mx1/mx1_camera_fiq.S b/arch/arm/mach-mx1/mx1_camera_fiq.S
deleted file mode 100644
index 9c69aa65bf17..000000000000
--- a/arch/arm/mach-mx1/mx1_camera_fiq.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
3 *
4 * Based on linux/arch/arm/lib/floppydma.S
5 * Copyright (C) 1995, 1996 Russell King
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/linkage.h>
12#include <asm/assembler.h>
13
14 .text
15 .global mx1_camera_sof_fiq_end
16 .global mx1_camera_sof_fiq_start
17mx1_camera_sof_fiq_start:
18 @ enable dma
19 ldr r12, [r9]
20 orr r12, r12, #0x00000001
21 str r12, [r9]
22 @ unmask DMA interrupt
23 ldr r12, [r8]
24 bic r12, r12, r13
25 str r12, [r8]
26 @ disable SOF interrupt
27 ldr r12, [r10]
28 bic r12, r12, #0x00010000
29 str r12, [r10]
30 @ clear SOF flag
31 mov r12, #0x00010000
32 str r12, [r11]
33 @ return from FIQ
34 subs pc, lr, #4
35mx1_camera_sof_fiq_end:
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 07:56:30 -0500