Merge branch 'mvebu/fixes' into mvebu/soc-cpuidle

7 files changed, 67 insertions, 25 deletions

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index e5ab3a7cb3d2..8e3b5f12cd7c 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -10,6 +10,7 @@ config ARCH_MVEBU
         select ZONE_DMA if ARM_LPAE
         select ARCH_REQUIRE_GPIOLIB
         select PCI_QUIRKS if PCI
+        select OF_ADDRESS_PCI
 
 if ARCH_MVEBU
 
@@ -19,6 +20,7 @@ config MACH_MVEBU_V7
         bool
         select ARMADA_370_XP_TIMER
         select CACHE_L2X0
+        select ARM_CPU_SUSPEND
 
 config MACH_ARMADA_370
         bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 90bcd5327312..bc7689e530a4 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -7,7 +7,7 @@ CFLAGS_pmsu.o			:= -march=armv7-a
 obj-y                            += system-controller.o mvebu-soc-id.o
 
 ifeq ($(CONFIG_MACH_MVEBU_V7),y)
-obj-y                            += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o
+obj-y                            += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
 endif
 
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index a04675e2ec99..f244622ffc00 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -23,6 +23,7 @@
 #include <linux/mbus.h>
 #include <linux/signal.h>
 #include <linux/slab.h>
+#include <linux/irqchip.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -71,17 +72,23 @@ static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
         return 1;
 }
 
-static void __init mvebu_timer_and_clk_init(void)
+static void __init mvebu_init_irq(void)
 {
-        of_clk_init(NULL);
-        clocksource_of_init();
+        irqchip_init();
         mvebu_scu_enable();
         coherency_init();
         BUG_ON(mvebu_mbus_dt_init(coherency_available()));
+}
+
+static void __init external_abort_quirk(void)
+{
+        u32 dev, rev;
 
-        if (of_machine_is_compatible("marvell,armada375"))
-                hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
-                                "imprecise external abort");
+        if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
+                return;
+
+        hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
+                        "imprecise external abort");
 }
 
 static void __init i2c_quirk(void)
@@ -178,8 +185,10 @@ static void __init mvebu_dt_init(void)
 {
         if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
                 i2c_quirk();
-        if (of_machine_is_compatible("marvell,a375-db"))
+        if (of_machine_is_compatible("marvell,a375-db")) {
+                external_abort_quirk();
                 thermal_quirk();
+        }
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
@@ -194,7 +203,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
         .l2c_aux_mask   = ~0,
         .smp            = smp_ops(armada_xp_smp_ops),
         .init_machine   = mvebu_dt_init,
-        .init_time      = mvebu_timer_and_clk_init,
+        .init_irq       = mvebu_init_irq,
         .restart        = mvebu_restart,
         .dt_compat      = armada_370_xp_dt_compat,
 MACHINE_END
@@ -207,7 +216,7 @@ static const char * const armada_375_dt_compat[] = {
 DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
         .l2c_aux_val    = 0,
         .l2c_aux_mask   = ~0,
-        .init_time      = mvebu_timer_and_clk_init,
+        .init_irq       = mvebu_init_irq,
         .init_machine   = mvebu_dt_init,
         .restart        = mvebu_restart,
         .dt_compat      = armada_375_dt_compat,
@@ -222,7 +231,7 @@ static const char * const armada_38x_dt_compat[] = {
 DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
         .l2c_aux_val    = 0,
         .l2c_aux_mask   = ~0,
-        .init_time      = mvebu_timer_and_clk_init,
+        .init_irq       = mvebu_init_irq,
         .restart        = mvebu_restart,
         .dt_compat      = armada_38x_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 477202fd39cc..2bdc3233abe2 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -292,6 +292,10 @@ static struct notifier_block mvebu_hwcc_nb = {
         .notifier_call = mvebu_hwcc_notifier,
 };
 
+static struct notifier_block mvebu_hwcc_pci_nb = {
+        .notifier_call = mvebu_hwcc_notifier,
+};
+
 static void __init armada_370_coherency_init(struct device_node *np)
 {
         struct resource res;
@@ -427,7 +431,7 @@ static int __init coherency_pci_init(void)
 {
         if (coherency_available())
                 bus_register_notifier(&pci_bus_type,
-                                       &mvebu_hwcc_nb);
+                                       &mvebu_hwcc_pci_nb);
         return 0;
 }
 
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index 5925366bc03c..da5bb292b91c 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -15,6 +15,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/assembler.h>
+
         __CPUINIT
 #define CPU_RESUME_ADDR_REG 0xf10182d4
 
@@ -22,13 +24,18 @@
 .global armada_375_smp_cpu1_enable_code_end
 
 armada_375_smp_cpu1_enable_code_start:
-        ldr     r0, [pc, #4]
+ARM_BE8(setend  be)
+        adr     r0, 1f
+        ldr     r0, [r0]
         ldr     r1, [r0]
+ARM_BE8(rev     r1, r1)
         mov     pc, r1
+1:
         .word   CPU_RESUME_ADDR_REG
 armada_375_smp_cpu1_enable_code_end:
 
 ENTRY(mvebu_cortex_a9_secondary_startup)
+ARM_BE8(setend  be)
         bl      v7_invalidate_l1
         b       secondary_startup
 ENDPROC(mvebu_cortex_a9_secondary_startup)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 9c819d65b337..b31a8293a347 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -66,6 +66,8 @@ static void __iomem *pmsu_mp_base;
 extern void ll_disable_coherency(void);
 extern void ll_enable_coherency(void);
 
+extern void armada_370_xp_cpu_resume(void);
+
 static struct platform_device armada_xp_cpuidle_device = {
         .name = "cpuidle-armada-370-xp",
 };
@@ -140,13 +142,6 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
         writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
 }
 
-static void armada_370_xp_cpu_resume(void)
-{
-        asm volatile("bl    ll_add_cpu_to_smp_group\n\t"
-                     "bl    ll_enable_coherency\n\t"
-                     "b     cpu_resume\n\t");
-}
-
 /* No locking is needed because we only access per-CPU registers */
 int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
 {
@@ -201,12 +196,12 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
 
         /* Test the CR_C bit and set it if it was cleared */
         asm volatile(
-        "mrc    p15, 0, %0, c1, c0, 0 \n\t"
-        "tst    %0, #(1 << 2) \n\t"
-        "orreq  %0, %0, #(1 << 2) \n\t"
-        "mcreq  p15, 0, %0, c1, c0, 0 \n\t"
+        "mrc    p15, 0, r0, c1, c0, 0 \n\t"
+        "tst    r0, #(1 << 2) \n\t"
+        "orreq  r0, r0, #(1 << 2) \n\t"
+        "mcreq  p15, 0, r0, c1, c0, 0 \n\t"
         "isb    "
-        : : "r" (0));
+        : : : "r0");
 
         pr_warn("Failed to suspend the system\n");
 
diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
new file mode 100644
index 000000000000..fc3de68d8c54
--- /dev/null
+++ b/arch/arm/mach-mvebu/pmsu_ll.S
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Gregory Clement <gregory.clement@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * This is the entry point through which CPUs exiting cpuidle deep
+ * idle state are going.
+ */
+ENTRY(armada_370_xp_cpu_resume)
+ARM_BE8(setend  be )                    @ go BE8 if entered LE
+        bl      ll_add_cpu_to_smp_group
+        bl      ll_enable_coherency
+        b       cpu_resume
+ENDPROC(armada_370_xp_cpu_resume)
+