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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-06 16:30:06 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-06 16:30:06 -0400
commitb4b50fd78b1e31989940dfc647e64453d0f7176a (patch)
tree1a55f110e021c02963b63759f3f18ea7ba3aa228 /arch/arm/mach-mvebu/platsmp.c
parentdccfd1e439c11422d7aca0d834b0430d24650e85 (diff)
parentf97c43bbdf8a1ea42477b1a804a48e7e368cb13c (diff)
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson: "This branch contains mostly additions and changes to platform enablement and SoC-level drivers. Since there's sometimes a dependency on device-tree changes, there's also a fair amount of those in this branch. Pieces worth mentioning are: - Mbus driver for Marvell platforms, allowing kernel configuration and resource allocation of on-chip peripherals. - Enablement of the mbus infrastructure from Marvell PCI-e drivers. - Preparation of MSI support for Marvell platforms. - Addition of new PCI-e host controller driver for Tegra platforms - Some churn caused by sharing of macro names between i.MX 6Q and 6DL platforms in the device tree sources and header files. - Various suspend/PM updates for Tegra, including LP1 support. - Versatile Express support for MCPM, part of big little support. - Allwinner platform support for A20 and A31 SoCs (dual and quad Cortex-A7) - OMAP2+ support for DRA7, a new Cortex-A15-based SoC. The code that touches other architectures are patches moving MSI arch-specific functions over to weak symbols and removal of ARCH_SUPPORTS_MSI, acked by PCI maintainers" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits) tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list ARM: dts: vf610-twr: enable i2c0 device ARM: dts: i.MX51: Add one more I2C2 pinmux entry ARM: dts: i.MX51: Move pins configuration under "iomuxc" label ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX ARM: dts: i.MX27: Disable AUDMUX in the template ARM: dts: wandboard: Add support for SDIO bcm4329 ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template ARM: dts: imx53-qsb: Make USBH1 functional ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module ARM: dts: imx6qdl-sabresd: Add touchscreen support ARM: imx: add ocram clock for imx53 ARM: dts: imx: ocram size is different between imx6q and imx6dl ARM: dts: imx27-phytec-phycore-som: Fix regulator settings ARM: dts: i.MX27: Remove clock name from CPU node ...
Diffstat (limited to 'arch/arm/mach-mvebu/platsmp.c')
-rw-r--r--arch/arm/mach-mvebu/platsmp.c25
1 files changed, 24 insertions, 1 deletions
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index f9c09b75d4d7..ff69c2df298b 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -21,6 +21,7 @@
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/of.h> 23#include <linux/of.h>
24#include <linux/of_address.h>
24#include <linux/mbus.h> 25#include <linux/mbus.h>
25#include <asm/cacheflush.h> 26#include <asm/cacheflush.h>
26#include <asm/smp_plat.h> 27#include <asm/smp_plat.h>
@@ -29,6 +30,9 @@
29#include "pmsu.h" 30#include "pmsu.h"
30#include "coherency.h" 31#include "coherency.h"
31 32
33#define AXP_BOOTROM_BASE 0xfff00000
34#define AXP_BOOTROM_SIZE 0x100000
35
32static struct clk *__init get_cpu_clk(int cpu) 36static struct clk *__init get_cpu_clk(int cpu)
33{ 37{
34 struct clk *cpu_clk; 38 struct clk *cpu_clk;
@@ -92,10 +96,29 @@ static void __init armada_xp_smp_init_cpus(void)
92 96
93void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) 97void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
94{ 98{
99 struct device_node *node;
100 struct resource res;
101 int err;
102
95 set_secondary_cpus_clock(); 103 set_secondary_cpus_clock();
96 flush_cache_all(); 104 flush_cache_all();
97 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); 105 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
98 mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M); 106
107 /*
108 * In order to boot the secondary CPUs we need to ensure
109 * the bootROM is mapped at the correct address.
110 */
111 node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
112 if (!node)
113 panic("Cannot find 'marvell,bootrom' compatible node");
114
115 err = of_address_to_resource(node, 0, &res);
116 if (err < 0)
117 panic("Cannot get 'bootrom' node address");
118
119 if (res.start != AXP_BOOTROM_BASE ||
120 resource_size(&res) != AXP_BOOTROM_SIZE)
121 panic("The address for the BootROM is incorrect");
99} 122}
100 123
101struct smp_operations armada_xp_smp_ops __initdata = { 124struct smp_operations armada_xp_smp_ops __initdata = {