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authorOlof Johansson <olof@lixom.net>2012-10-04 23:17:25 -0400
committerOlof Johansson <olof@lixom.net>2012-10-04 23:17:25 -0400
commit54d69df5849ec2e660aa12ac75562618c10fb499 (patch)
treeadbfb8bcc7cc73b83bf2b784fa331911ba03573a /arch/arm/mach-mv78xx0
parentad932bb6b549722a561fb31ac2fa50dcbcb3e36b (diff)
parent46f2007c1efadfa4071c17e75f140c47f09293de (diff)
Merge branch 'late/kirkwood' into late/soc
Merge in the late Kirkwood branch with the OMAP late branch for upstream submission. Final contents described in shared tag. Fixup remove/change conflicts in arch/arm/mach-omap2/devices.c and drivers/spi/spi-omap2-mcspi.c. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-mv78xx0')
-rw-r--r--arch/arm/mach-mv78xx0/addr-map.c9
-rw-r--r--arch/arm/mach-mv78xx0/common.c13
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/bridge-regs.h12
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/io.h24
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/mv78xx0.h105
-rw-r--r--arch/arm/mach-mv78xx0/irq.c10
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c122
7 files changed, 112 insertions, 183 deletions
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index a9bc84180d21..343c435b4176 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -13,6 +13,7 @@
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <plat/addr-map.h> 15#include <plat/addr-map.h>
16#include <mach/mv78xx0.h>
16#include "common.h" 17#include "common.h"
17 18
18/* 19/*
@@ -47,7 +48,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
47 * so we don't need to take that into account here. 48 * so we don't need to take that into account here.
48 */ 49 */
49 50
50 return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); 51 return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
51} 52}
52 53
53/* 54/*
@@ -71,17 +72,17 @@ void __init mv78xx0_setup_cpu_mbus(void)
71 */ 72 */
72 if (mv78xx0_core_index() == 0) 73 if (mv78xx0_core_index() == 0)
73 orion_setup_cpu_mbus_target(&addr_map_cfg, 74 orion_setup_cpu_mbus_target(&addr_map_cfg,
74 DDR_WINDOW_CPU0_BASE); 75 (void __iomem *) DDR_WINDOW_CPU0_BASE);
75 else 76 else
76 orion_setup_cpu_mbus_target(&addr_map_cfg, 77 orion_setup_cpu_mbus_target(&addr_map_cfg,
77 DDR_WINDOW_CPU1_BASE); 78 (void __iomem *) DDR_WINDOW_CPU1_BASE);
78} 79}
79 80
80void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, 81void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
81 int maj, int min) 82 int maj, int min)
82{ 83{
83 orion_setup_cpu_win(&addr_map_cfg, window, base, size, 84 orion_setup_cpu_win(&addr_map_cfg, window, base, size,
84 TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); 85 TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
85} 86}
86 87
87void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, 88void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 3057f7d4329a..131cd4883f3d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -20,8 +20,8 @@
20#include <mach/mv78xx0.h> 20#include <mach/mv78xx0.h>
21#include <mach/bridge-regs.h> 21#include <mach/bridge-regs.h>
22#include <plat/cache-feroceon-l2.h> 22#include <plat/cache-feroceon-l2.h>
23#include <plat/ehci-orion.h> 23#include <linux/platform_data/usb-ehci-orion.h>
24#include <plat/orion_nand.h> 24#include <linux/platform_data/mtd-orion_nand.h>
25#include <plat/time.h> 25#include <plat/time.h>
26#include <plat/common.h> 26#include <plat/common.h>
27#include <plat/addr-map.h> 27#include <plat/addr-map.h>
@@ -130,17 +130,12 @@ static int get_tclk(void)
130 ****************************************************************************/ 130 ****************************************************************************/
131static struct map_desc mv78xx0_io_desc[] __initdata = { 131static struct map_desc mv78xx0_io_desc[] __initdata = {
132 { 132 {
133 .virtual = MV78XX0_CORE_REGS_VIRT_BASE, 133 .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
134 .pfn = 0, 134 .pfn = 0,
135 .length = MV78XX0_CORE_REGS_SIZE, 135 .length = MV78XX0_CORE_REGS_SIZE,
136 .type = MT_DEVICE, 136 .type = MT_DEVICE,
137 }, { 137 }, {
138 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), 138 .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
139 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
140 .length = MV78XX0_PCIE_IO_SIZE * 8,
141 .type = MT_DEVICE,
142 }, {
143 .virtual = MV78XX0_REGS_VIRT_BASE,
144 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), 139 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
145 .length = MV78XX0_REGS_SIZE, 140 .length = MV78XX0_REGS_SIZE,
146 .type = MT_DEVICE, 141 .type = MT_DEVICE,
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index eb187e0e059b..5f03484584d4 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -11,18 +11,18 @@
11 11
12#include <mach/mv78xx0.h> 12#include <mach/mv78xx0.h>
13 13
14#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) 14#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
15#define L2_WRITETHROUGH 0x00020000 15#define L2_WRITETHROUGH 0x00020000
16 16
17#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) 17#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
18#define SOFT_RESET_OUT_EN 0x00000004 18#define SOFT_RESET_OUT_EN 0x00000004
19 19
20#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) 20#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
21#define SOFT_RESET 0x00000001 21#define SOFT_RESET 0x00000001
22 22
23#define BRIDGE_INT_TIMER1_CLR (~0x0004) 23#define BRIDGE_INT_TIMER1_CLR (~0x0004)
24 24
25#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) 25#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
26#define IRQ_CAUSE_ERR_OFF 0x0000 26#define IRQ_CAUSE_ERR_OFF 0x0000
27#define IRQ_CAUSE_LOW_OFF 0x0004 27#define IRQ_CAUSE_LOW_OFF 0x0004
28#define IRQ_CAUSE_HIGH_OFF 0x0008 28#define IRQ_CAUSE_HIGH_OFF 0x0008
@@ -30,7 +30,7 @@
30#define IRQ_MASK_LOW_OFF 0x0010 30#define IRQ_MASK_LOW_OFF 0x0010
31#define IRQ_MASK_HIGH_OFF 0x0014 31#define IRQ_MASK_HIGH_OFF 0x0014
32 32
33#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) 33#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
34#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) 34#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
35 35
36#endif 36#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
deleted file mode 100644
index c7d9d00d8fc1..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/mach-mv78xx0/include/mach/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "mv78xx0.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
19 + MV78XX0_PCIE_IO_VIRT_BASE(0));
20}
21
22#define __io(a) __io(a)
23
24#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index e807c4c52a0b..46200a183cf2 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -29,28 +29,27 @@
29 * 29 *
30 * virt phys size 30 * virt phys size
31 * fe400000 f102x000 16K core-specific peripheral registers 31 * fe400000 f102x000 16K core-specific peripheral registers
32 * fe700000 f0800000 1M PCIe #0 I/O space 32 * fee00000 f0800000 64K PCIe #0 I/O space
33 * fe800000 f0900000 1M PCIe #1 I/O space 33 * fee10000 f0900000 64K PCIe #1 I/O space
34 * fe900000 f0a00000 1M PCIe #2 I/O space 34 * fee20000 f0a00000 64K PCIe #2 I/O space
35 * fea00000 f0b00000 1M PCIe #3 I/O space 35 * fee30000 f0b00000 64K PCIe #3 I/O space
36 * feb00000 f0c00000 1M PCIe #4 I/O space 36 * fee40000 f0c00000 64K PCIe #4 I/O space
37 * fec00000 f0d00000 1M PCIe #5 I/O space 37 * fee50000 f0d00000 64K PCIe #5 I/O space
38 * fed00000 f0e00000 1M PCIe #6 I/O space 38 * fee60000 f0e00000 64K PCIe #6 I/O space
39 * fee00000 f0f00000 1M PCIe #7 I/O space 39 * fee70000 f0f00000 64K PCIe #7 I/O space
40 * fef00000 f1000000 1M on-chip peripheral registers 40 * fd000000 f1000000 1M on-chip peripheral registers
41 */ 41 */
42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 44#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 45#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
46#define MV78XX0_CORE_REGS_SIZE SZ_16K 46#define MV78XX0_CORE_REGS_SIZE SZ_16K
47 47
48#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) 48#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
49#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
50#define MV78XX0_PCIE_IO_SIZE SZ_1M 49#define MV78XX0_PCIE_IO_SIZE SZ_1M
51 50
52#define MV78XX0_REGS_PHYS_BASE 0xf1000000 51#define MV78XX0_REGS_PHYS_BASE 0xf1000000
53#define MV78XX0_REGS_VIRT_BASE 0xfef00000 52#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000)
54#define MV78XX0_REGS_SIZE SZ_1M 53#define MV78XX0_REGS_SIZE SZ_1M
55 54
56#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
@@ -65,47 +64,47 @@
65/* 64/*
66 * Register Map 65 * Register Map
67 */ 66 */
68#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) 67#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
69#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) 68#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500)
70#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) 69#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570)
71 70
72#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) 71#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
73#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) 72#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
74#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) 73#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
75#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) 74#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
76#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) 75#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
77#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) 76#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
78#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) 77#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
79#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) 78#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
80#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) 79#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
81#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) 80#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
82#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) 81#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
83#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) 82#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
84#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) 83#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
85#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) 84#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
86#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) 85#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
87 86
88#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) 87#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
89#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) 88#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
90 89
91#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) 90#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
92#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) 91#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
93#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) 92#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
94#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) 93#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
95 94
96#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) 95#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
97#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) 96#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
98#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) 97#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
99 98
100#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) 99#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
101#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) 100#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
102 101
103#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) 102#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
104#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) 103#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
105#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) 104#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
106#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) 105#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
107 106
108#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) 107#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
109 108
110/* 109/*
111 * Supported devices and revisions. 110 * Supported devices and revisions.
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index eff9a750bbe2..32073444024b 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -10,7 +10,9 @@
10#include <linux/gpio.h> 10#include <linux/gpio.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/io.h>
13#include <mach/bridge-regs.h> 14#include <mach/bridge-regs.h>
15#include <plat/orion-gpio.h>
14#include <plat/irq.h> 16#include <plat/irq.h>
15#include "common.h" 17#include "common.h"
16 18
@@ -23,16 +25,16 @@ static int __initdata gpio0_irqs[4] = {
23 25
24void __init mv78xx0_init_irq(void) 26void __init mv78xx0_init_irq(void)
25{ 27{
26 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); 28 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
27 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 29 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
28 orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); 30 orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
29 31
30 /* 32 /*
31 * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask 33 * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
32 * registers for core #1 are at an offset of 0x18 from those of 34 * registers for core #1 are at an offset of 0x18 from those of
33 * core #0.) 35 * core #0.)
34 */ 36 */
35 orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 37 orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
36 mv78xx0_core_index() ? 0x18 : 0, 38 mv78xx0_core_index() ? 0x18 : 0,
37 IRQ_MV78XX0_GPIO_START, gpio0_irqs); 39 IRQ_MV78XX0_GPIO_START, gpio0_irqs);
38} 40}
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 2e56e86b6d68..a9a154a646dd 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -15,6 +15,7 @@
15#include <asm/mach/pci.h> 15#include <asm/mach/pci.h>
16#include <plat/pcie.h> 16#include <plat/pcie.h>
17#include <plat/addr-map.h> 17#include <plat/addr-map.h>
18#include <mach/mv78xx0.h>
18#include "common.h" 19#include "common.h"
19 20
20struct pcie_port { 21struct pcie_port {
@@ -23,119 +24,73 @@ struct pcie_port {
23 u8 root_bus_nr; 24 u8 root_bus_nr;
24 void __iomem *base; 25 void __iomem *base;
25 spinlock_t conf_lock; 26 spinlock_t conf_lock;
26 char io_space_name[16];
27 char mem_space_name[16]; 27 char mem_space_name[16];
28 struct resource res[2]; 28 struct resource res;
29}; 29};
30 30
31static struct pcie_port pcie_port[8]; 31static struct pcie_port pcie_port[8];
32static int num_pcie_ports; 32static int num_pcie_ports;
33static struct resource pcie_io_space; 33static struct resource pcie_io_space;
34static struct resource pcie_mem_space;
35
36 34
37void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) 35void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
38{ 36{
39 *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE); 37 *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
40 *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); 38 *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
41} 39}
42 40
41u32 pcie_port_size[8] = {
42 0,
43 0x30000000,
44 0x10000000,
45 0x10000000,
46 0x08000000,
47 0x08000000,
48 0x08000000,
49 0x04000000,
50};
51
43static void __init mv78xx0_pcie_preinit(void) 52static void __init mv78xx0_pcie_preinit(void)
44{ 53{
45 int i; 54 int i;
46 u32 size_each; 55 u32 size_each;
47 u32 start; 56 u32 start;
48 int win; 57 int win = 0;
49 58
50 pcie_io_space.name = "PCIe I/O Space"; 59 pcie_io_space.name = "PCIe I/O Space";
51 pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); 60 pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
52 pcie_io_space.end = 61 pcie_io_space.end =
53 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; 62 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
54 pcie_io_space.flags = IORESOURCE_IO; 63 pcie_io_space.flags = IORESOURCE_MEM;
55 if (request_resource(&iomem_resource, &pcie_io_space)) 64 if (request_resource(&iomem_resource, &pcie_io_space))
56 panic("can't allocate PCIe I/O space"); 65 panic("can't allocate PCIe I/O space");
57 66
58 pcie_mem_space.name = "PCIe MEM Space"; 67 if (num_pcie_ports > 7)
59 pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; 68 panic("invalid number of PCIe ports");
60 pcie_mem_space.end = 69
61 MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; 70 size_each = pcie_port_size[num_pcie_ports];
62 pcie_mem_space.flags = IORESOURCE_MEM;
63 if (request_resource(&iomem_resource, &pcie_mem_space))
64 panic("can't allocate PCIe MEM space");
65 71
72 start = MV78XX0_PCIE_MEM_PHYS_BASE;
66 for (i = 0; i < num_pcie_ports; i++) { 73 for (i = 0; i < num_pcie_ports; i++) {
67 struct pcie_port *pp = pcie_port + i; 74 struct pcie_port *pp = pcie_port + i;
68 75
69 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
70 "PCIe %d.%d I/O", pp->maj, pp->min);
71 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
72 pp->res[0].name = pp->io_space_name;
73 pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
74 pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
75 pp->res[0].flags = IORESOURCE_IO;
76
77 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), 76 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
78 "PCIe %d.%d MEM", pp->maj, pp->min); 77 "PCIe %d.%d MEM", pp->maj, pp->min);
79 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; 78 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
80 pp->res[1].name = pp->mem_space_name; 79 pp->res.name = pp->mem_space_name;
81 pp->res[1].flags = IORESOURCE_MEM; 80 pp->res.flags = IORESOURCE_MEM;
82 } 81 pp->res.start = start;
83 82 pp->res.end = start + size_each - 1;
84 switch (num_pcie_ports) {
85 case 0:
86 size_each = 0;
87 break;
88
89 case 1:
90 size_each = 0x30000000;
91 break;
92
93 case 2 ... 3:
94 size_each = 0x10000000;
95 break;
96
97 case 4 ... 6:
98 size_each = 0x08000000;
99 break;
100
101 case 7:
102 size_each = 0x04000000;
103 break;
104
105 default:
106 panic("invalid number of PCIe ports");
107 }
108
109 start = MV78XX0_PCIE_MEM_PHYS_BASE;
110 for (i = 0; i < num_pcie_ports; i++) {
111 struct pcie_port *pp = pcie_port + i;
112
113 pp->res[1].start = start;
114 pp->res[1].end = start + size_each - 1;
115 start += size_each; 83 start += size_each;
116 }
117
118 for (i = 0; i < num_pcie_ports; i++) {
119 struct pcie_port *pp = pcie_port + i;
120 84
121 if (request_resource(&pcie_io_space, &pp->res[0])) 85 if (request_resource(&iomem_resource, &pp->res))
122 panic("can't allocate PCIe I/O sub-space");
123
124 if (request_resource(&pcie_mem_space, &pp->res[1]))
125 panic("can't allocate PCIe MEM sub-space"); 86 panic("can't allocate PCIe MEM sub-space");
126 }
127 87
128 win = 0; 88 mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
129 for (i = 0; i < num_pcie_ports; i++) { 89 resource_size(&pp->res),
130 struct pcie_port *pp = pcie_port + i; 90 pp->maj, pp->min);
131 91
132 mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, 92 mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
133 resource_size(&pp->res[0]),
134 pp->maj, pp->min); 93 pp->maj, pp->min);
135
136 mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
137 resource_size(&pp->res[1]),
138 pp->maj, pp->min);
139 } 94 }
140} 95}
141 96
@@ -156,8 +111,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
156 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 111 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
157 orion_pcie_setup(pp->base); 112 orion_pcie_setup(pp->base);
158 113
159 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); 114 pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
160 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); 115
116 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
161 117
162 return 1; 118 return 1;
163} 119}
@@ -267,11 +223,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
267 .map_irq = mv78xx0_pcie_map_irq, 223 .map_irq = mv78xx0_pcie_map_irq,
268}; 224};
269 225
270static void __init add_pcie_port(int maj, int min, unsigned long base) 226static void __init add_pcie_port(int maj, int min, void __iomem *base)
271{ 227{
272 printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); 228 printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
273 229
274 if (orion_pcie_link_up((void __iomem *)base)) { 230 if (orion_pcie_link_up(base)) {
275 struct pcie_port *pp = &pcie_port[num_pcie_ports++]; 231 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
276 232
277 printk("link up\n"); 233 printk("link up\n");
@@ -279,9 +235,9 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
279 pp->maj = maj; 235 pp->maj = maj;
280 pp->min = min; 236 pp->min = min;
281 pp->root_bus_nr = -1; 237 pp->root_bus_nr = -1;
282 pp->base = (void __iomem *)base; 238 pp->base = base;
283 spin_lock_init(&pp->conf_lock); 239 spin_lock_init(&pp->conf_lock);
284 memset(pp->res, 0, sizeof(pp->res)); 240 memset(&pp->res, 0, sizeof(pp->res));
285 } else { 241 } else {
286 printk("link down, ignoring\n"); 242 printk("link down, ignoring\n");
287 } 243 }
@@ -293,7 +249,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
293 249
294 if (init_port0) { 250 if (init_port0) {
295 add_pcie_port(0, 0, PCIE00_VIRT_BASE); 251 add_pcie_port(0, 0, PCIE00_VIRT_BASE);
296 if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { 252 if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
297 add_pcie_port(0, 1, PCIE01_VIRT_BASE); 253 add_pcie_port(0, 1, PCIE01_VIRT_BASE);
298 add_pcie_port(0, 2, PCIE02_VIRT_BASE); 254 add_pcie_port(0, 2, PCIE02_VIRT_BASE);
299 add_pcie_port(0, 3, PCIE03_VIRT_BASE); 255 add_pcie_port(0, 3, PCIE03_VIRT_BASE);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 05:16:57 -0500