diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-07-17 16:25:03 -0400 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2012-07-17 16:25:03 -0400 |
commit | 45bcc91aca328ba33f39cd711cf70b46ddd41ba0 (patch) | |
tree | e2cf2730ea8181e61b04f57760c49f0c13772669 /arch/arm/mach-mv78xx0 | |
parent | f923c8e887d6eed9f14937b8e09a8f5a7d5941d5 (diff) | |
parent | 0da47184eafe0eb3ddb1340a70f8a150b477b6a0 (diff) |
Merge branch 'clps711x/cleanup' into next/cleanup
Patches from Alexander Shiyan <shc_work@mail.ru>:
* clps711x/cleanup:
ARM: clps711x: Remove the setting of the time
ARM: clps711x: Removed superfluous transform virt_to_bus and related functions
ARM: clps711x/p720t: Replace __initcall by .init_early call
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-mv78xx0')
-rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h index c64dbb96dbad..eb187e0e059b 100644 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | |||
@@ -31,5 +31,6 @@ | |||
31 | #define IRQ_MASK_HIGH_OFF 0x0014 | 31 | #define IRQ_MASK_HIGH_OFF 0x0014 |
32 | 32 | ||
33 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | 33 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) |
34 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) | ||
34 | 35 | ||
35 | #endif | 36 | #endif |
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index 3674497162e3..e807c4c52a0b 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
@@ -42,6 +42,7 @@ | |||
42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 | 42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 |
43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 | 43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 |
44 | #define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 | 44 | #define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 |
45 | #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 | ||
45 | #define MV78XX0_CORE_REGS_SIZE SZ_16K | 46 | #define MV78XX0_CORE_REGS_SIZE SZ_16K |
46 | 47 | ||
47 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) | 48 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) |
@@ -59,6 +60,7 @@ | |||
59 | * Core-specific peripheral registers. | 60 | * Core-specific peripheral registers. |
60 | */ | 61 | */ |
61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) | 62 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) |
63 | #define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) | ||
62 | 64 | ||
63 | /* | 65 | /* |
64 | * Register Map | 66 | * Register Map |