diff options
author | Andrew Lunn <andrew@lunn.ch> | 2012-06-29 03:25:58 -0400 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2012-07-04 04:37:34 -0400 |
commit | 1e0c1ce00d83834d03f4d8d039734ca4703298df (patch) | |
tree | 8ca81565e79af2a55679d27f75b8a8d44da4feac /arch/arm/mach-mv78xx0 | |
parent | d19550e5b8aecf6e4b93bfeeb3e8be70e49f5b0e (diff) |
ARM: Orion: Fix WDT compile for Dove and MV78xx0
Commit 0fa1f0609a0c1fe8b2be3c0089a2cb48f7fda521 (ARM: Orion: Fix
Virtual/Physical mixup with watchdog) broke the Dove & MV78xx0
build. Although these two SoC don't use the watchdog, the shared
platform code still needs to build. Add the necessary defines.
Cc: stable@vger.kernel.org
Reported-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-mv78xx0')
-rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h index c64dbb96dbad..eb187e0e059b 100644 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | |||
@@ -31,5 +31,6 @@ | |||
31 | #define IRQ_MASK_HIGH_OFF 0x0014 | 31 | #define IRQ_MASK_HIGH_OFF 0x0014 |
32 | 32 | ||
33 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | 33 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) |
34 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) | ||
34 | 35 | ||
35 | #endif | 36 | #endif |
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index 3674497162e3..e807c4c52a0b 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
@@ -42,6 +42,7 @@ | |||
42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 | 42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 |
43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 | 43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 |
44 | #define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 | 44 | #define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 |
45 | #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 | ||
45 | #define MV78XX0_CORE_REGS_SIZE SZ_16K | 46 | #define MV78XX0_CORE_REGS_SIZE SZ_16K |
46 | 47 | ||
47 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) | 48 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) |
@@ -59,6 +60,7 @@ | |||
59 | * Core-specific peripheral registers. | 60 | * Core-specific peripheral registers. |
60 | */ | 61 | */ |
61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) | 62 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) |
63 | #define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) | ||
62 | 64 | ||
63 | /* | 65 | /* |
64 | * Register Map | 66 | * Register Map |