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| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2009-05-08 21:29:27 -0400 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2009-05-08 21:29:27 -0400 |
| commit | d585a021c0b10b0477d6b608c53e1feb8cde0507 (patch) | |
| tree | 5ca059da1db7f15d4b29427644ad9c08270c885c /arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |
| parent | 84e5b0d00f8f84c4ae226be131d4bebbcee88bd3 (diff) | |
| parent | 091bf7624d1c90cec9e578a18529f615213ff847 (diff) | |
Merge commit 'v2.6.30-rc5' into next
Diffstat (limited to 'arch/arm/mach-mv78xx0/include/mach/mv78xx0.h')
| -rw-r--r-- | arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 32 |
1 files changed, 13 insertions, 19 deletions
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e930ea5330a2..d715b92b0908 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
| @@ -59,25 +59,6 @@ | |||
| 59 | * Core-specific peripheral registers. | 59 | * Core-specific peripheral registers. |
| 60 | */ | 60 | */ |
| 61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) | 61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) |
| 62 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | ||
| 63 | #define L2_WRITETHROUGH 0x00020000 | ||
| 64 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
| 65 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
| 66 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
| 67 | #define SOFT_RESET 0x00000001 | ||
| 68 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
| 69 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
| 70 | #define BRIDGE_INT_TIMER0 0x0002 | ||
| 71 | #define BRIDGE_INT_TIMER1 0x0004 | ||
| 72 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
| 73 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
| 74 | #define IRQ_CAUSE_ERR_OFF 0x0000 | ||
| 75 | #define IRQ_CAUSE_LOW_OFF 0x0004 | ||
| 76 | #define IRQ_CAUSE_HIGH_OFF 0x0008 | ||
| 77 | #define IRQ_MASK_ERR_OFF 0x000c | ||
| 78 | #define IRQ_MASK_LOW_OFF 0x0010 | ||
| 79 | #define IRQ_MASK_HIGH_OFF 0x0014 | ||
| 80 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
| 81 | 62 | ||
| 82 | /* | 63 | /* |
| 83 | * Register Map | 64 | * Register Map |
| @@ -90,6 +71,8 @@ | |||
| 90 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) | 71 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) |
| 91 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) | 72 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) |
| 92 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) | 73 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) |
| 74 | #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) | ||
| 75 | #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) | ||
| 93 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | 76 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) |
| 94 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | 77 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) |
| 95 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | 78 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) |
| @@ -121,5 +104,16 @@ | |||
| 121 | 104 | ||
| 122 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) | 105 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) |
| 123 | 106 | ||
| 107 | /* | ||
| 108 | * Supported devices and revisions. | ||
| 109 | */ | ||
| 110 | #define MV78X00_Z0_DEV_ID 0x6381 | ||
| 111 | #define MV78X00_REV_Z0 1 | ||
| 112 | |||
| 113 | #define MV78100_DEV_ID 0x7810 | ||
| 114 | #define MV78100_REV_A0 1 | ||
| 115 | |||
| 116 | #define MV78200_DEV_ID 0x7820 | ||
| 117 | #define MV78200_REV_A0 1 | ||
| 124 | 118 | ||
| 125 | #endif | 119 | #endif |