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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-05 16:51:19 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-05 16:51:19 -0400
commitdfc25e4503aef6b82a1de4a0fbe19aafa8648fbe (patch)
tree0a4f3a07e2286918298e635186e42726f4658cbd /arch/arm/mach-msm
parent9f800363bb0ea459e15bef0928a72c88d374e489 (diff)
parent8f881c67368f82d0e20e1072b50b21132cc2440d (diff)
Merge tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann: "These cleanup patches are mainly move stuff around and should all be harmless. They are mainly split out so that other branches can be based on top to avoid conflicts. Notable changes are: - We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no longer used (Uwe Kleine-König) - The Qualcomm MSM platform is split out into legacy mach-msm and new-style mach-qcom, to allow easier maintainance of the new hardware support without regressions (Kumar Gala) - A rework of some of the Kconfig logic to simplify multiplatform support (Rob Herring) - Samsung Exynos gets closer to supporting multiplatform (Sachin Kamat and others) - mach-bcm3528 gets merged into mach-bcm (Stephen Warren) - at91 gains some common clock framework support (Alexandre Belloni, Jean-Jacques Hiblot and other French people)" * tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits) ARM: hisi: select HAVE_ARM_SCU only for SMP ARM: efm32: allow uncompress debug output ARM: prima2: build reset code standalone ARM: at91: add PWM clock ARM: at91: move sam9261 SoC to common clk ARM: at91: prepare common clk transition for sam9261 SoC ARM: at91: updated the at91_dt_defconfig with support for the ADS7846 ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs ARM: at91: dt: Add at91sam9261 dt SoC support ARM: at91: switch sam9rl to common clock framework ARM: at91/dt: define main clk frequency of at91sam9rlek ARM: at91/dt: define at91sam9rl clocks ARM: at91: prepare common clk transition for sam9rl SoCs ARM: at91: prepare sam9 dt boards transition to common clk ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs ARM: at91: Add at91sam9rl DT SoC support ARM: at91: prepare at91sam9rl DT transition ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig ...
Diffstat (limited to 'arch/arm/mach-msm')
-rw-r--r--arch/arm/mach-msm/Kconfig54
-rw-r--r--arch/arm/mach-msm/Makefile8
-rw-r--r--arch/arm/mach-msm/board-dt.c41
-rw-r--r--arch/arm/mach-msm/common.h1
-rw-r--r--arch/arm/mach-msm/headsmp.S39
-rw-r--r--arch/arm/mach-msm/hotplug.c74
-rw-r--r--arch/arm/mach-msm/include/mach/timex.h21
-rw-r--r--arch/arm/mach-msm/platsmp.c161
-rw-r--r--arch/arm/mach-msm/scm-boot.c39
-rw-r--r--arch/arm/mach-msm/scm-boot.h22
-rw-r--r--arch/arm/mach-msm/scm.c299
-rw-r--r--arch/arm/mach-msm/scm.h25
-rw-r--r--arch/arm/mach-msm/timer.c333
13 files changed, 5 insertions, 1112 deletions
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 9625cf378931..a7f959e58c3d 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,50 +1,9 @@
1config ARCH_MSM
2 bool
3
4config ARCH_MSM_DT
5 bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7
6 select ARCH_MSM
7 select ARCH_REQUIRE_GPIOLIB
8 select CLKSRC_OF
9 select GENERIC_CLOCKEVENTS
10 help
11 Support for Qualcomm's devicetree based MSM systems.
12
13if ARCH_MSM 1if ARCH_MSM
14 2
15menu "Qualcomm MSM SoC Selection"
16 depends on ARCH_MSM_DT
17
18config ARCH_MSM8X60
19 bool "Enable support for MSM8X60"
20 select ARM_GIC
21 select CPU_V7
22 select HAVE_SMP
23 select MSM_SCM if SMP
24 select MSM_TIMER
25
26config ARCH_MSM8960
27 bool "Enable support for MSM8960"
28 select ARM_GIC
29 select CPU_V7
30 select HAVE_SMP
31 select MSM_SCM if SMP
32 select MSM_TIMER
33
34config ARCH_MSM8974
35 bool "Enable support for MSM8974"
36 select ARM_GIC
37 select CPU_V7
38 select HAVE_ARM_ARCH_TIMER
39 select HAVE_SMP
40 select MSM_SCM if SMP
41
42endmenu
43
44choice 3choice
45 prompt "Qualcomm MSM SoC Type" 4 prompt "Qualcomm MSM SoC Type"
46 default ARCH_MSM7X00A 5 default ARCH_MSM7X00A
47 depends on ARCH_MSM_NODT 6 depends on ARCH_MSM
48 7
49config ARCH_MSM7X00A 8config ARCH_MSM7X00A
50 bool "MSM7x00A / MSM7x01A" 9 bool "MSM7x00A / MSM7x01A"
@@ -54,7 +13,7 @@ config ARCH_MSM7X00A
54 select MACH_TROUT if !MACH_HALIBUT 13 select MACH_TROUT if !MACH_HALIBUT
55 select MSM_PROC_COMM 14 select MSM_PROC_COMM
56 select MSM_SMD 15 select MSM_SMD
57 select MSM_TIMER 16 select CLKSRC_QCOM
58 select MSM_SMD_PKG3 17 select MSM_SMD_PKG3
59 18
60config ARCH_MSM7X30 19config ARCH_MSM7X30
@@ -66,7 +25,7 @@ config ARCH_MSM7X30
66 select MSM_GPIOMUX 25 select MSM_GPIOMUX
67 select MSM_PROC_COMM 26 select MSM_PROC_COMM
68 select MSM_SMD 27 select MSM_SMD
69 select MSM_TIMER 28 select CLKSRC_QCOM
70 select MSM_VIC 29 select MSM_VIC
71 30
72config ARCH_QSD8X50 31config ARCH_QSD8X50
@@ -78,7 +37,7 @@ config ARCH_QSD8X50
78 select MSM_GPIOMUX 37 select MSM_GPIOMUX
79 select MSM_PROC_COMM 38 select MSM_PROC_COMM
80 select MSM_SMD 39 select MSM_SMD
81 select MSM_TIMER 40 select CLKSRC_QCOM
82 select MSM_VIC 41 select MSM_VIC
83 42
84endchoice 43endchoice
@@ -99,7 +58,7 @@ config MSM_VIC
99 bool 58 bool
100 59
101menu "Qualcomm MSM Board Type" 60menu "Qualcomm MSM Board Type"
102 depends on ARCH_MSM_NODT 61 depends on ARCH_MSM
103 62
104config MACH_HALIBUT 63config MACH_HALIBUT
105 depends on ARCH_MSM 64 depends on ARCH_MSM
@@ -153,7 +112,4 @@ config MSM_GPIOMUX
153config MSM_SCM 112config MSM_SCM
154 bool 113 bool
155 114
156config MSM_TIMER
157 bool
158
159endif 115endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 8e307a10d3c3..27c078a568df 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,4 +1,3 @@
1obj-$(CONFIG_MSM_TIMER) += timer.o
2obj-$(CONFIG_MSM_PROC_COMM) += clock.o 1obj-$(CONFIG_MSM_PROC_COMM) += clock.o
3 2
4obj-$(CONFIG_MSM_VIC) += irq-vic.o 3obj-$(CONFIG_MSM_VIC) += irq-vic.o
@@ -14,18 +13,11 @@ obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
14 13
15obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o 14obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
16obj-$(CONFIG_MSM_SMD) += last_radio_log.o 15obj-$(CONFIG_MSM_SMD) += last_radio_log.o
17obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
18
19CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
20
21obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
22obj-$(CONFIG_SMP) += headsmp.o platsmp.o
23 16
24obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o 17obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
25obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o 18obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
26obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o 19obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
27obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o 20obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
28obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o 21obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
29obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o
30obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o 22obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
31obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o 23obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-msm/board-dt.c
deleted file mode 100644
index 1f11d93e700e..000000000000
--- a/arch/arm/mach-msm/board-dt.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/of.h>
15#include <linux/of_platform.h>
16
17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
19
20#include "common.h"
21
22static const char * const msm_dt_match[] __initconst = {
23 "qcom,msm8660-fluid",
24 "qcom,msm8660-surf",
25 "qcom,msm8960-cdp",
26 NULL
27};
28
29static const char * const apq8074_dt_match[] __initconst = {
30 "qcom,apq8074-dragonboard",
31 NULL
32};
33
34DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
35 .smp = smp_ops(msm_smp_ops),
36 .dt_compat = msm_dt_match,
37MACHINE_END
38
39DT_MACHINE_START(APQ_DT, "Qualcomm MSM (Flattened Device Tree)")
40 .dt_compat = apq8074_dt_match,
41MACHINE_END
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index 33c7725adae2..0a4899b7d85c 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -24,7 +24,6 @@ extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
24 unsigned int mtype, void *caller); 24 unsigned int mtype, void *caller);
25 25
26extern struct smp_operations msm_smp_ops; 26extern struct smp_operations msm_smp_ops;
27extern void msm_cpu_die(unsigned int cpu);
28 27
29struct msm_mmc_platform_data; 28struct msm_mmc_platform_data;
30 29
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
deleted file mode 100644
index 6c62c3f82fe6..000000000000
--- a/arch/arm/mach-msm/headsmp.S
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * linux/arch/arm/mach-realview/headsmp.S
3 *
4 * Copyright (c) 2003 ARM Limited
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13
14/*
15 * MSM specific entry point for secondary CPUs. This provides
16 * a "holding pen" into which all secondary cores are held until we're
17 * ready for them to initialise.
18 */
19ENTRY(msm_secondary_startup)
20 mrc p15, 0, r0, c0, c0, 5
21 and r0, r0, #15
22 adr r4, 1f
23 ldmia r4, {r5, r6}
24 sub r4, r4, r5
25 add r6, r6, r4
26pen: ldr r7, [r6]
27 cmp r7, r0
28 bne pen
29
30 /*
31 * we've been released from the holding pen: secondary_stack
32 * should now contain the SVC stack for this core
33 */
34 b secondary_startup
35ENDPROC(msm_secondary_startup)
36
37 .align
381: .long .
39 .long pen_release
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
deleted file mode 100644
index 326a87261f9a..000000000000
--- a/arch/arm/mach-msm/hotplug.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * Copyright (C) 2002 ARM Ltd.
3 * All Rights Reserved
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/kernel.h>
10#include <linux/errno.h>
11#include <linux/smp.h>
12
13#include <asm/smp_plat.h>
14
15#include "common.h"
16
17static inline void cpu_enter_lowpower(void)
18{
19}
20
21static inline void cpu_leave_lowpower(void)
22{
23}
24
25static inline void platform_do_lowpower(unsigned int cpu)
26{
27 /* Just enter wfi for now. TODO: Properly shut off the cpu. */
28 for (;;) {
29 /*
30 * here's the WFI
31 */
32 asm("wfi"
33 :
34 :
35 : "memory", "cc");
36
37 if (pen_release == cpu_logical_map(cpu)) {
38 /*
39 * OK, proper wakeup, we're done
40 */
41 break;
42 }
43
44 /*
45 * getting here, means that we have come out of WFI without
46 * having been woken up - this shouldn't happen
47 *
48 * The trouble is, letting people know about this is not really
49 * possible, since we are currently running incoherently, and
50 * therefore cannot safely call printk() or anything else
51 */
52 pr_debug("CPU%u: spurious wakeup call\n", cpu);
53 }
54}
55
56/*
57 * platform-specific code to shutdown a CPU
58 *
59 * Called with IRQs disabled
60 */
61void __ref msm_cpu_die(unsigned int cpu)
62{
63 /*
64 * we're ready for shutdown now, so do it
65 */
66 cpu_enter_lowpower();
67 platform_do_lowpower(cpu);
68
69 /*
70 * bring this CPU back into the world of cache
71 * coherency, and then restore interrupts
72 */
73 cpu_leave_lowpower();
74}
diff --git a/arch/arm/mach-msm/include/mach/timex.h b/arch/arm/mach-msm/include/mach/timex.h
deleted file mode 100644
index a62e6b215aec..000000000000
--- a/arch/arm/mach-msm/include/mach/timex.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/* arch/arm/mach-msm/include/mach/timex.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MSM_TIMEX_H
17#define __ASM_ARCH_MSM_TIMEX_H
18
19#define CLOCK_TICK_RATE 1000000
20
21#endif
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
deleted file mode 100644
index f10a1f58fde9..000000000000
--- a/arch/arm/mach-msm/platsmp.c
+++ /dev/null
@@ -1,161 +0,0 @@
1/*
2 * Copyright (C) 2002 ARM Ltd.
3 * All Rights Reserved
4 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/errno.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/jiffies.h>
16#include <linux/smp.h>
17#include <linux/io.h>
18
19#include <asm/cacheflush.h>
20#include <asm/cputype.h>
21#include <asm/mach-types.h>
22#include <asm/smp_plat.h>
23
24#include "scm-boot.h"
25#include "common.h"
26
27#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
28#define SCSS_CPU1CORE_RESET 0xD80
29#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
30
31extern void msm_secondary_startup(void);
32
33static DEFINE_SPINLOCK(boot_lock);
34
35static inline int get_core_count(void)
36{
37 /* 1 + the PART[1:0] field of MIDR */
38 return ((read_cpuid_id() >> 4) & 3) + 1;
39}
40
41static void msm_secondary_init(unsigned int cpu)
42{
43 /*
44 * let the primary processor know we're out of the
45 * pen, then head off into the C entry point
46 */
47 pen_release = -1;
48 smp_wmb();
49
50 /*
51 * Synchronise with the boot thread.
52 */
53 spin_lock(&boot_lock);
54 spin_unlock(&boot_lock);
55}
56
57static void prepare_cold_cpu(unsigned int cpu)
58{
59 int ret;
60 ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
61 SCM_FLAG_COLDBOOT_CPU1);
62 if (ret == 0) {
63 void __iomem *sc1_base_ptr;
64 sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
65 if (sc1_base_ptr) {
66 writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
67 writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
68 writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
69 iounmap(sc1_base_ptr);
70 }
71 } else
72 printk(KERN_DEBUG "Failed to set secondary core boot "
73 "address\n");
74}
75
76static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
77{
78 unsigned long timeout;
79 static int cold_boot_done;
80
81 /* Only need to bring cpu out of reset this way once */
82 if (cold_boot_done == false) {
83 prepare_cold_cpu(cpu);
84 cold_boot_done = true;
85 }
86
87 /*
88 * set synchronisation state between this boot processor
89 * and the secondary one
90 */
91 spin_lock(&boot_lock);
92
93 /*
94 * The secondary processor is waiting to be released from
95 * the holding pen - release it, then wait for it to flag
96 * that it has been released by resetting pen_release.
97 *
98 * Note that "pen_release" is the hardware CPU ID, whereas
99 * "cpu" is Linux's internal ID.
100 */
101 pen_release = cpu_logical_map(cpu);
102 sync_cache_w(&pen_release);
103
104 /*
105 * Send the secondary CPU a soft interrupt, thereby causing
106 * the boot monitor to read the system wide flags register,
107 * and branch to the address found there.
108 */
109 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
110
111 timeout = jiffies + (1 * HZ);
112 while (time_before(jiffies, timeout)) {
113 smp_rmb();
114 if (pen_release == -1)
115 break;
116
117 udelay(10);
118 }
119
120 /*
121 * now the secondary core is starting up let it run its
122 * calibrations, then wait for it to finish
123 */
124 spin_unlock(&boot_lock);
125
126 return pen_release != -1 ? -ENOSYS : 0;
127}
128
129/*
130 * Initialise the CPU possible map early - this describes the CPUs
131 * which may be present or become present in the system. The msm8x60
132 * does not support the ARM SCU, so just set the possible cpu mask to
133 * NR_CPUS.
134 */
135static void __init msm_smp_init_cpus(void)
136{
137 unsigned int i, ncores = get_core_count();
138
139 if (ncores > nr_cpu_ids) {
140 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
141 ncores, nr_cpu_ids);
142 ncores = nr_cpu_ids;
143 }
144
145 for (i = 0; i < ncores; i++)
146 set_cpu_possible(i, true);
147}
148
149static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
150{
151}
152
153struct smp_operations msm_smp_ops __initdata = {
154 .smp_init_cpus = msm_smp_init_cpus,
155 .smp_prepare_cpus = msm_smp_prepare_cpus,
156 .smp_secondary_init = msm_secondary_init,
157 .smp_boot_secondary = msm_boot_secondary,
158#ifdef CONFIG_HOTPLUG_CPU
159 .cpu_die = msm_cpu_die,
160#endif
161};
diff --git a/arch/arm/mach-msm/scm-boot.c b/arch/arm/mach-msm/scm-boot.c
deleted file mode 100644
index 45cee3e469a5..000000000000
--- a/arch/arm/mach-msm/scm-boot.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#include <linux/module.h>
19#include <linux/slab.h>
20
21#include "scm.h"
22#include "scm-boot.h"
23
24/*
25 * Set the cold/warm boot address for one of the CPU cores.
26 */
27int scm_set_boot_addr(phys_addr_t addr, int flags)
28{
29 struct {
30 unsigned int flags;
31 phys_addr_t addr;
32 } cmd;
33
34 cmd.addr = addr;
35 cmd.flags = flags;
36 return scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR,
37 &cmd, sizeof(cmd), NULL, 0);
38}
39EXPORT_SYMBOL(scm_set_boot_addr);
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h
deleted file mode 100644
index 7be32ff5d687..000000000000
--- a/arch/arm/mach-msm/scm-boot.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef __MACH_SCM_BOOT_H
13#define __MACH_SCM_BOOT_H
14
15#define SCM_BOOT_ADDR 0x1
16#define SCM_FLAG_COLDBOOT_CPU1 0x1
17#define SCM_FLAG_WARMBOOT_CPU1 0x2
18#define SCM_FLAG_WARMBOOT_CPU0 0x4
19
20int scm_set_boot_addr(phys_addr_t addr, int flags);
21
22#endif
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c
deleted file mode 100644
index c536fd6bf827..000000000000
--- a/arch/arm/mach-msm/scm.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#include <linux/slab.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/mutex.h>
22#include <linux/errno.h>
23#include <linux/err.h>
24
25#include <asm/cacheflush.h>
26
27#include "scm.h"
28
29/* Cache line size for msm8x60 */
30#define CACHELINESIZE 32
31
32#define SCM_ENOMEM -5
33#define SCM_EOPNOTSUPP -4
34#define SCM_EINVAL_ADDR -3
35#define SCM_EINVAL_ARG -2
36#define SCM_ERROR -1
37#define SCM_INTERRUPTED 1
38
39static DEFINE_MUTEX(scm_lock);
40
41/**
42 * struct scm_command - one SCM command buffer
43 * @len: total available memory for command and response
44 * @buf_offset: start of command buffer
45 * @resp_hdr_offset: start of response buffer
46 * @id: command to be executed
47 * @buf: buffer returned from scm_get_command_buffer()
48 *
49 * An SCM command is laid out in memory as follows:
50 *
51 * ------------------- <--- struct scm_command
52 * | command header |
53 * ------------------- <--- scm_get_command_buffer()
54 * | command buffer |
55 * ------------------- <--- struct scm_response and
56 * | response header | scm_command_to_response()
57 * ------------------- <--- scm_get_response_buffer()
58 * | response buffer |
59 * -------------------
60 *
61 * There can be arbitrary padding between the headers and buffers so
62 * you should always use the appropriate scm_get_*_buffer() routines
63 * to access the buffers in a safe manner.
64 */
65struct scm_command {
66 u32 len;
67 u32 buf_offset;
68 u32 resp_hdr_offset;
69 u32 id;
70 u32 buf[0];
71};
72
73/**
74 * struct scm_response - one SCM response buffer
75 * @len: total available memory for response
76 * @buf_offset: start of response data relative to start of scm_response
77 * @is_complete: indicates if the command has finished processing
78 */
79struct scm_response {
80 u32 len;
81 u32 buf_offset;
82 u32 is_complete;
83};
84
85/**
86 * alloc_scm_command() - Allocate an SCM command
87 * @cmd_size: size of the command buffer
88 * @resp_size: size of the response buffer
89 *
90 * Allocate an SCM command, including enough room for the command
91 * and response headers as well as the command and response buffers.
92 *
93 * Returns a valid &scm_command on success or %NULL if the allocation fails.
94 */
95static struct scm_command *alloc_scm_command(size_t cmd_size, size_t resp_size)
96{
97 struct scm_command *cmd;
98 size_t len = sizeof(*cmd) + sizeof(struct scm_response) + cmd_size +
99 resp_size;
100
101 cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL);
102 if (cmd) {
103 cmd->len = len;
104 cmd->buf_offset = offsetof(struct scm_command, buf);
105 cmd->resp_hdr_offset = cmd->buf_offset + cmd_size;
106 }
107 return cmd;
108}
109
110/**
111 * free_scm_command() - Free an SCM command
112 * @cmd: command to free
113 *
114 * Free an SCM command.
115 */
116static inline void free_scm_command(struct scm_command *cmd)
117{
118 kfree(cmd);
119}
120
121/**
122 * scm_command_to_response() - Get a pointer to a scm_response
123 * @cmd: command
124 *
125 * Returns a pointer to a response for a command.
126 */
127static inline struct scm_response *scm_command_to_response(
128 const struct scm_command *cmd)
129{
130 return (void *)cmd + cmd->resp_hdr_offset;
131}
132
133/**
134 * scm_get_command_buffer() - Get a pointer to a command buffer
135 * @cmd: command
136 *
137 * Returns a pointer to the command buffer of a command.
138 */
139static inline void *scm_get_command_buffer(const struct scm_command *cmd)
140{
141 return (void *)cmd->buf;
142}
143
144/**
145 * scm_get_response_buffer() - Get a pointer to a response buffer
146 * @rsp: response
147 *
148 * Returns a pointer to a response buffer of a response.
149 */
150static inline void *scm_get_response_buffer(const struct scm_response *rsp)
151{
152 return (void *)rsp + rsp->buf_offset;
153}
154
155static int scm_remap_error(int err)
156{
157 switch (err) {
158 case SCM_ERROR:
159 return -EIO;
160 case SCM_EINVAL_ADDR:
161 case SCM_EINVAL_ARG:
162 return -EINVAL;
163 case SCM_EOPNOTSUPP:
164 return -EOPNOTSUPP;
165 case SCM_ENOMEM:
166 return -ENOMEM;
167 }
168 return -EINVAL;
169}
170
171static u32 smc(u32 cmd_addr)
172{
173 int context_id;
174 register u32 r0 asm("r0") = 1;
175 register u32 r1 asm("r1") = (u32)&context_id;
176 register u32 r2 asm("r2") = cmd_addr;
177 do {
178 asm volatile(
179 __asmeq("%0", "r0")
180 __asmeq("%1", "r0")
181 __asmeq("%2", "r1")
182 __asmeq("%3", "r2")
183#ifdef REQUIRES_SEC
184 ".arch_extension sec\n"
185#endif
186 "smc #0 @ switch to secure world\n"
187 : "=r" (r0)
188 : "r" (r0), "r" (r1), "r" (r2)
189 : "r3");
190 } while (r0 == SCM_INTERRUPTED);
191
192 return r0;
193}
194
195static int __scm_call(const struct scm_command *cmd)
196{
197 int ret;
198 u32 cmd_addr = virt_to_phys(cmd);
199
200 /*
201 * Flush the entire cache here so callers don't have to remember
202 * to flush the cache when passing physical addresses to the secure
203 * side in the buffer.
204 */
205 flush_cache_all();
206 ret = smc(cmd_addr);
207 if (ret < 0)
208 ret = scm_remap_error(ret);
209
210 return ret;
211}
212
213/**
214 * scm_call() - Send an SCM command
215 * @svc_id: service identifier
216 * @cmd_id: command identifier
217 * @cmd_buf: command buffer
218 * @cmd_len: length of the command buffer
219 * @resp_buf: response buffer
220 * @resp_len: length of the response buffer
221 *
222 * Sends a command to the SCM and waits for the command to finish processing.
223 */
224int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
225 void *resp_buf, size_t resp_len)
226{
227 int ret;
228 struct scm_command *cmd;
229 struct scm_response *rsp;
230
231 cmd = alloc_scm_command(cmd_len, resp_len);
232 if (!cmd)
233 return -ENOMEM;
234
235 cmd->id = (svc_id << 10) | cmd_id;
236 if (cmd_buf)
237 memcpy(scm_get_command_buffer(cmd), cmd_buf, cmd_len);
238
239 mutex_lock(&scm_lock);
240 ret = __scm_call(cmd);
241 mutex_unlock(&scm_lock);
242 if (ret)
243 goto out;
244
245 rsp = scm_command_to_response(cmd);
246 do {
247 u32 start = (u32)rsp;
248 u32 end = (u32)scm_get_response_buffer(rsp) + resp_len;
249 start &= ~(CACHELINESIZE - 1);
250 while (start < end) {
251 asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
252 : "memory");
253 start += CACHELINESIZE;
254 }
255 } while (!rsp->is_complete);
256
257 if (resp_buf)
258 memcpy(resp_buf, scm_get_response_buffer(rsp), resp_len);
259out:
260 free_scm_command(cmd);
261 return ret;
262}
263EXPORT_SYMBOL(scm_call);
264
265u32 scm_get_version(void)
266{
267 int context_id;
268 static u32 version = -1;
269 register u32 r0 asm("r0");
270 register u32 r1 asm("r1");
271
272 if (version != -1)
273 return version;
274
275 mutex_lock(&scm_lock);
276
277 r0 = 0x1 << 8;
278 r1 = (u32)&context_id;
279 do {
280 asm volatile(
281 __asmeq("%0", "r0")
282 __asmeq("%1", "r1")
283 __asmeq("%2", "r0")
284 __asmeq("%3", "r1")
285#ifdef REQUIRES_SEC
286 ".arch_extension sec\n"
287#endif
288 "smc #0 @ switch to secure world\n"
289 : "=r" (r0), "=r" (r1)
290 : "r" (r0), "r" (r1)
291 : "r2", "r3");
292 } while (r0 == SCM_INTERRUPTED);
293
294 version = r1;
295 mutex_unlock(&scm_lock);
296
297 return version;
298}
299EXPORT_SYMBOL(scm_get_version);
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-msm/scm.h
deleted file mode 100644
index 00b31ea58f29..000000000000
--- a/arch/arm/mach-msm/scm.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef __MACH_SCM_H
13#define __MACH_SCM_H
14
15#define SCM_SVC_BOOT 0x1
16#define SCM_SVC_PIL 0x2
17
18extern int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
19 void *resp_buf, size_t resp_len);
20
21#define SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
22
23extern u32 scm_get_version(void);
24
25#endif
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
deleted file mode 100644
index fd1644987534..000000000000
--- a/arch/arm/mach-msm/timer.c
+++ /dev/null
@@ -1,333 +0,0 @@
1/*
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/clocksource.h>
18#include <linux/clockchips.h>
19#include <linux/cpu.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/sched_clock.h>
28
29#include <asm/mach/time.h>
30
31#include "common.h"
32
33#define TIMER_MATCH_VAL 0x0000
34#define TIMER_COUNT_VAL 0x0004
35#define TIMER_ENABLE 0x0008
36#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
37#define TIMER_ENABLE_EN BIT(0)
38#define TIMER_CLEAR 0x000C
39#define DGT_CLK_CTL 0x10
40#define DGT_CLK_CTL_DIV_4 0x3
41#define TIMER_STS_GPT0_CLR_PEND BIT(10)
42
43#define GPT_HZ 32768
44
45#define MSM_DGT_SHIFT 5
46
47static void __iomem *event_base;
48static void __iomem *sts_base;
49
50static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
51{
52 struct clock_event_device *evt = dev_id;
53 /* Stop the timer tick */
54 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
55 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
56 ctrl &= ~TIMER_ENABLE_EN;
57 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
58 }
59 evt->event_handler(evt);
60 return IRQ_HANDLED;
61}
62
63static int msm_timer_set_next_event(unsigned long cycles,
64 struct clock_event_device *evt)
65{
66 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
67
68 ctrl &= ~TIMER_ENABLE_EN;
69 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
70
71 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
72 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
73
74 if (sts_base)
75 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
76 cpu_relax();
77
78 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
79 return 0;
80}
81
82static void msm_timer_set_mode(enum clock_event_mode mode,
83 struct clock_event_device *evt)
84{
85 u32 ctrl;
86
87 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
88 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
89
90 switch (mode) {
91 case CLOCK_EVT_MODE_RESUME:
92 case CLOCK_EVT_MODE_PERIODIC:
93 break;
94 case CLOCK_EVT_MODE_ONESHOT:
95 /* Timer is enabled in set_next_event */
96 break;
97 case CLOCK_EVT_MODE_UNUSED:
98 case CLOCK_EVT_MODE_SHUTDOWN:
99 break;
100 }
101 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
102}
103
104static struct clock_event_device __percpu *msm_evt;
105
106static void __iomem *source_base;
107
108static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
109{
110 return readl_relaxed(source_base + TIMER_COUNT_VAL);
111}
112
113static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
114{
115 /*
116 * Shift timer count down by a constant due to unreliable lower bits
117 * on some targets.
118 */
119 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
120}
121
122static struct clocksource msm_clocksource = {
123 .name = "dg_timer",
124 .rating = 300,
125 .read = msm_read_timer_count,
126 .mask = CLOCKSOURCE_MASK(32),
127 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
128};
129
130static int msm_timer_irq;
131static int msm_timer_has_ppi;
132
133static int msm_local_timer_setup(struct clock_event_device *evt)
134{
135 int cpu = smp_processor_id();
136 int err;
137
138 evt->irq = msm_timer_irq;
139 evt->name = "msm_timer";
140 evt->features = CLOCK_EVT_FEAT_ONESHOT;
141 evt->rating = 200;
142 evt->set_mode = msm_timer_set_mode;
143 evt->set_next_event = msm_timer_set_next_event;
144 evt->cpumask = cpumask_of(cpu);
145
146 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
147
148 if (msm_timer_has_ppi) {
149 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
150 } else {
151 err = request_irq(evt->irq, msm_timer_interrupt,
152 IRQF_TIMER | IRQF_NOBALANCING |
153 IRQF_TRIGGER_RISING, "gp_timer", evt);
154 if (err)
155 pr_err("request_irq failed\n");
156 }
157
158 return 0;
159}
160
161static void msm_local_timer_stop(struct clock_event_device *evt)
162{
163 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
164 disable_percpu_irq(evt->irq);
165}
166
167static int msm_timer_cpu_notify(struct notifier_block *self,
168 unsigned long action, void *hcpu)
169{
170 /*
171 * Grab cpu pointer in each case to avoid spurious
172 * preemptible warnings
173 */
174 switch (action & ~CPU_TASKS_FROZEN) {
175 case CPU_STARTING:
176 msm_local_timer_setup(this_cpu_ptr(msm_evt));
177 break;
178 case CPU_DYING:
179 msm_local_timer_stop(this_cpu_ptr(msm_evt));
180 break;
181 }
182
183 return NOTIFY_OK;
184}
185
186static struct notifier_block msm_timer_cpu_nb = {
187 .notifier_call = msm_timer_cpu_notify,
188};
189
190static u64 notrace msm_sched_clock_read(void)
191{
192 return msm_clocksource.read(&msm_clocksource);
193}
194
195static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
196 bool percpu)
197{
198 struct clocksource *cs = &msm_clocksource;
199 int res = 0;
200
201 msm_timer_irq = irq;
202 msm_timer_has_ppi = percpu;
203
204 msm_evt = alloc_percpu(struct clock_event_device);
205 if (!msm_evt) {
206 pr_err("memory allocation failed for clockevents\n");
207 goto err;
208 }
209
210 if (percpu)
211 res = request_percpu_irq(irq, msm_timer_interrupt,
212 "gp_timer", msm_evt);
213
214 if (res) {
215 pr_err("request_percpu_irq failed\n");
216 } else {
217 res = register_cpu_notifier(&msm_timer_cpu_nb);
218 if (res) {
219 free_percpu_irq(irq, msm_evt);
220 goto err;
221 }
222
223 /* Immediately configure the timer on the boot CPU */
224 msm_local_timer_setup(__this_cpu_ptr(msm_evt));
225 }
226
227err:
228 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
229 res = clocksource_register_hz(cs, dgt_hz);
230 if (res)
231 pr_err("clocksource_register failed\n");
232 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
233}
234
235#ifdef CONFIG_OF
236static void __init msm_dt_timer_init(struct device_node *np)
237{
238 u32 freq;
239 int irq;
240 struct resource res;
241 u32 percpu_offset;
242 void __iomem *base;
243 void __iomem *cpu0_base;
244
245 base = of_iomap(np, 0);
246 if (!base) {
247 pr_err("Failed to map event base\n");
248 return;
249 }
250
251 /* We use GPT0 for the clockevent */
252 irq = irq_of_parse_and_map(np, 1);
253 if (irq <= 0) {
254 pr_err("Can't get irq\n");
255 return;
256 }
257
258 /* We use CPU0's DGT for the clocksource */
259 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
260 percpu_offset = 0;
261
262 if (of_address_to_resource(np, 0, &res)) {
263 pr_err("Failed to parse DGT resource\n");
264 return;
265 }
266
267 cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
268 if (!cpu0_base) {
269 pr_err("Failed to map source base\n");
270 return;
271 }
272
273 if (of_property_read_u32(np, "clock-frequency", &freq)) {
274 pr_err("Unknown frequency\n");
275 return;
276 }
277
278 event_base = base + 0x4;
279 sts_base = base + 0x88;
280 source_base = cpu0_base + 0x24;
281 freq /= 4;
282 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
283
284 msm_timer_init(freq, 32, irq, !!percpu_offset);
285}
286CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
287CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
288#endif
289
290static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
291 u32 sts)
292{
293 void __iomem *base;
294
295 base = ioremap(addr, SZ_256);
296 if (!base) {
297 pr_err("Failed to map timer base\n");
298 return -ENOMEM;
299 }
300 event_base = base + event;
301 source_base = base + source;
302 if (sts)
303 sts_base = base + sts;
304
305 return 0;
306}
307
308void __init msm7x01_timer_init(void)
309{
310 struct clocksource *cs = &msm_clocksource;
311
312 if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
313 return;
314 cs->read = msm_read_timer_count_shift;
315 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
316 /* 600 KHz */
317 msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
318 false);
319}
320
321void __init msm7x30_timer_init(void)
322{
323 if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
324 return;
325 msm_timer_init(24576000 / 4, 32, 1, false);
326}
327
328void __init qsd8x50_timer_init(void)
329{
330 if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
331 return;
332 msm_timer_init(19200000 / 4, 32, 7, false);
333}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 20:28:41 -0500