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authorStepan Moskovchenko <stepanm@codeaurora.org>2010-11-12 22:29:52 -0500
committerDaniel Walker <dwalker@codeaurora.org>2010-11-30 17:02:56 -0500
commite8952e3b32701817705b216b492a9be4fa5cbefc (patch)
tree6b69809d4ccaaee1df4676abdd3b75b3a57f7c6e /arch/arm/mach-msm
parentff25ff842ea6afd58ccc2e3f386ee5ac540b6a63 (diff)
msm: iommu: Support for the 2nd GFX core's IOMMU
Add the platform data and resources needed for the second 2D graphics core's IOMMU. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm')
-rw-r--r--arch/arm/mach-msm/devices-msm8x60-iommu.c54
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c
index 8cccb2680542..a6ecd39ae069 100644
--- a/arch/arm/mach-msm/devices-msm8x60-iommu.c
+++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c
@@ -254,6 +254,27 @@ static struct resource msm_iommu_gfx2d0_resources[] = {
254 }, 254 },
255}; 255};
256 256
257static struct resource msm_iommu_gfx2d1_resources[] = {
258 {
259 .start = MSM_IOMMU_GFX2D1_PHYS,
260 .end = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1,
261 .name = "physbase",
262 .flags = IORESOURCE_MEM,
263 },
264 {
265 .name = "nonsecure_irq",
266 .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
267 .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
268 .flags = IORESOURCE_IRQ,
269 },
270 {
271 .name = "secure_irq",
272 .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
273 .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
274 .flags = IORESOURCE_IRQ,
275 },
276};
277
257static struct platform_device msm_root_iommu_dev = { 278static struct platform_device msm_root_iommu_dev = {
258 .name = "msm_iommu", 279 .name = "msm_iommu",
259 .id = -1, 280 .id = -1,
@@ -307,6 +328,11 @@ static struct msm_iommu_dev gfx2d0_iommu = {
307 .clk_rate = 27000000 328 .clk_rate = 27000000
308}; 329};
309 330
331static struct msm_iommu_dev gfx2d1_iommu = {
332 .name = "gfx2d1",
333 .clk_rate = 27000000
334};
335
310static struct platform_device msm_device_iommu_jpegd = { 336static struct platform_device msm_device_iommu_jpegd = {
311 .name = "msm_iommu", 337 .name = "msm_iommu",
312 .id = 0, 338 .id = 0,
@@ -417,6 +443,16 @@ static struct platform_device msm_device_iommu_gfx2d0 = {
417 .resource = msm_iommu_gfx2d0_resources, 443 .resource = msm_iommu_gfx2d0_resources,
418}; 444};
419 445
446struct platform_device msm_device_iommu_gfx2d1 = {
447 .name = "msm_iommu",
448 .id = 11,
449 .dev = {
450 .parent = &msm_root_iommu_dev.dev,
451 },
452 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
453 .resource = msm_iommu_gfx2d1_resources,
454};
455
420static struct msm_iommu_ctx_dev jpegd_src_ctx = { 456static struct msm_iommu_ctx_dev jpegd_src_ctx = {
421 .name = "jpegd_src", 457 .name = "jpegd_src",
422 .num = 0, 458 .num = 0,
@@ -538,6 +574,12 @@ static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
538 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} 574 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
539}; 575};
540 576
577static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
578 .name = "gfx2d1_2d1",
579 .num = 0,
580 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
581};
582
541static struct platform_device msm_device_jpegd_src_ctx = { 583static struct platform_device msm_device_jpegd_src_ctx = {
542 .name = "msm_iommu_ctx", 584 .name = "msm_iommu_ctx",
543 .id = 0, 585 .id = 0,
@@ -698,6 +740,14 @@ static struct platform_device msm_device_gfx2d0_2d0_ctx = {
698 }, 740 },
699}; 741};
700 742
743static struct platform_device msm_device_gfx2d1_2d1_ctx = {
744 .name = "msm_iommu_ctx",
745 .id = 20,
746 .dev = {
747 .parent = &msm_device_iommu_gfx2d1.dev,
748 },
749};
750
701static struct platform_device *msm_iommu_devs[] = { 751static struct platform_device *msm_iommu_devs[] = {
702 &msm_device_iommu_jpegd, 752 &msm_device_iommu_jpegd,
703 &msm_device_iommu_vpe, 753 &msm_device_iommu_vpe,
@@ -710,6 +760,7 @@ static struct platform_device *msm_iommu_devs[] = {
710 &msm_device_iommu_vcodec_b, 760 &msm_device_iommu_vcodec_b,
711 &msm_device_iommu_gfx3d, 761 &msm_device_iommu_gfx3d,
712 &msm_device_iommu_gfx2d0, 762 &msm_device_iommu_gfx2d0,
763 &msm_device_iommu_gfx2d1,
713}; 764};
714 765
715static struct msm_iommu_dev *msm_iommu_data[] = { 766static struct msm_iommu_dev *msm_iommu_data[] = {
@@ -724,6 +775,7 @@ static struct msm_iommu_dev *msm_iommu_data[] = {
724 &vcodec_b_iommu, 775 &vcodec_b_iommu,
725 &gfx3d_iommu, 776 &gfx3d_iommu,
726 &gfx2d0_iommu, 777 &gfx2d0_iommu,
778 &gfx2d1_iommu,
727}; 779};
728 780
729static struct platform_device *msm_iommu_ctx_devs[] = { 781static struct platform_device *msm_iommu_ctx_devs[] = {
@@ -747,6 +799,7 @@ static struct platform_device *msm_iommu_ctx_devs[] = {
747 &msm_device_gfx3d_user_ctx, 799 &msm_device_gfx3d_user_ctx,
748 &msm_device_gfx3d_priv_ctx, 800 &msm_device_gfx3d_priv_ctx,
749 &msm_device_gfx2d0_2d0_ctx, 801 &msm_device_gfx2d0_2d0_ctx,
802 &msm_device_gfx2d1_2d1_ctx,
750}; 803};
751 804
752static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { 805static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
@@ -770,6 +823,7 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
770 &gfx3d_user_ctx, 823 &gfx3d_user_ctx,
771 &gfx3d_priv_ctx, 824 &gfx3d_priv_ctx,
772 &gfx2d0_2d0_ctx, 825 &gfx2d0_2d0_ctx,
826 &gfx2d1_2d1_ctx,
773}; 827};
774 828
775static int msm8x60_iommu_init(void) 829static int msm8x60_iommu_init(void)