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authorStepan Moskovchenko <stepanm@codeaurora.org>2010-11-12 22:29:47 -0500
committerDaniel Walker <dwalker@codeaurora.org>2010-11-30 16:53:08 -0500
commit23513c3b39207c569da2c8afdced62ec43b4a272 (patch)
tree6c0762b6fa42f3d1b95c8ba9f67da613b7975856 /arch/arm/mach-msm
parent70cc2c00d7471f21120befeb7fc107c856e3985b (diff)
msm: iommu: Increase maximum MID size to 5 bits
On msm8x60, the MID field on the AXI connection to the IOMMU can be up to five bits wide. Thus, allow the IOMMU context platform data to map up to 32 MIDs. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm')
-rw-r--r--arch/arm/mach-msm/include/mach/iommu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
index 218ef5732a24..17fc79fc8bc2 100644
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -26,7 +26,7 @@
26 * be present. These mappings are typically determined at design time and are 26 * be present. These mappings are typically determined at design time and are
27 * not expected to change at run time. 27 * not expected to change at run time.
28 */ 28 */
29#define MAX_NUM_MIDS 16 29#define MAX_NUM_MIDS 32
30 30
31/** 31/**
32 * struct msm_iommu_dev - a single IOMMU hardware instance 32 * struct msm_iommu_dev - a single IOMMU hardware instance