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authorStephen Boyd <sboyd@codeaurora.org>2011-11-08 13:34:08 -0500
committerDavid Brown <davidb@codeaurora.org>2011-11-10 13:36:33 -0500
commit2081a6b57fba2717fa4b04fe978abad238e1f9e4 (patch)
treedf2af31666b505eb4cf2a753b5917bbb6647fd94 /arch/arm/mach-msm
parent2a00c1068b2c1ae451e230ef8bd010d7b2f56f54 (diff)
msm: timer: Remove SoC specific #ifdefs
The timer frequency is currently ifdefed in addition to setting the DGT clock's divider value on SCORPIONMP targets. Setup the frequency dynamically using the existing cpu_is_*() branches and assign a custom clocksource read function for 7x01a to get the shift out of the generic path. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm')
-rw-r--r--arch/arm/mach-msm/timer.c38
1 files changed, 17 insertions, 21 deletions
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index fc0646442e09..ca0a957d8626 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -40,20 +40,7 @@
40 40
41#define GPT_HZ 32768 41#define GPT_HZ 32768
42 42
43/* TODO: Remove these ifdefs */ 43#define MSM_DGT_SHIFT 5
44#if defined(CONFIG_ARCH_QSD8X50)
45#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
46#define MSM_DGT_SHIFT (0)
47#elif defined(CONFIG_ARCH_MSM7X30)
48#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
49#define MSM_DGT_SHIFT (0)
50#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
51#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
52#define MSM_DGT_SHIFT (0)
53#else
54#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
55#define MSM_DGT_SHIFT (5)
56#endif
57 44
58static void __iomem *event_base; 45static void __iomem *event_base;
59 46
@@ -123,18 +110,23 @@ static void __iomem *source_base;
123 110
124static cycle_t msm_read_timer_count(struct clocksource *cs) 111static cycle_t msm_read_timer_count(struct clocksource *cs)
125{ 112{
113 return readl_relaxed(source_base + TIMER_COUNT_VAL);
114}
115
116static cycle_t msm_read_timer_count_shift(struct clocksource *cs)
117{
126 /* 118 /*
127 * Shift timer count down by a constant due to unreliable lower bits 119 * Shift timer count down by a constant due to unreliable lower bits
128 * on some targets. 120 * on some targets.
129 */ 121 */
130 return readl_relaxed(source_base + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT; 122 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
131} 123}
132 124
133static struct clocksource msm_clocksource = { 125static struct clocksource msm_clocksource = {
134 .name = "dg_timer", 126 .name = "dg_timer",
135 .rating = 300, 127 .rating = 300,
136 .read = msm_read_timer_count, 128 .read = msm_read_timer_count,
137 .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), 129 .mask = CLOCKSOURCE_MASK(32),
138 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 130 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
139}; 131};
140 132
@@ -143,27 +135,31 @@ static void __init msm_timer_init(void)
143 struct clock_event_device *ce = &msm_clockevent; 135 struct clock_event_device *ce = &msm_clockevent;
144 struct clocksource *cs = &msm_clocksource; 136 struct clocksource *cs = &msm_clocksource;
145 int res; 137 int res;
138 u32 dgt_hz;
146 139
147 if (cpu_is_msm7x01()) { 140 if (cpu_is_msm7x01()) {
148 event_base = MSM_CSR_BASE; 141 event_base = MSM_CSR_BASE;
149 source_base = MSM_CSR_BASE + 0x10; 142 source_base = MSM_CSR_BASE + 0x10;
143 dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
144 cs->read = msm_read_timer_count_shift;
145 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
150 } else if (cpu_is_msm7x30()) { 146 } else if (cpu_is_msm7x30()) {
151 event_base = MSM_CSR_BASE + 0x04; 147 event_base = MSM_CSR_BASE + 0x04;
152 source_base = MSM_CSR_BASE + 0x24; 148 source_base = MSM_CSR_BASE + 0x24;
149 dgt_hz = 24576000 / 4;
153 } else if (cpu_is_qsd8x50()) { 150 } else if (cpu_is_qsd8x50()) {
154 event_base = MSM_CSR_BASE; 151 event_base = MSM_CSR_BASE;
155 source_base = MSM_CSR_BASE + 0x10; 152 source_base = MSM_CSR_BASE + 0x10;
153 dgt_hz = 19200000 / 4;
156 } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { 154 } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
157 event_base = MSM_TMR_BASE + 0x04; 155 event_base = MSM_TMR_BASE + 0x04;
158 /* Use CPU0's timer as the global clock source. */ 156 /* Use CPU0's timer as the global clock source. */
159 source_base = MSM_TMR0_BASE + 0x24; 157 source_base = MSM_TMR0_BASE + 0x24;
158 dgt_hz = 27000000 / 4;
159 writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
160 } else 160 } else
161 BUG(); 161 BUG();
162 162
163#ifdef CONFIG_ARCH_MSM_SCORPIONMP
164 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
165#endif
166
167 writel_relaxed(0, event_base + TIMER_ENABLE); 163 writel_relaxed(0, event_base + TIMER_ENABLE);
168 writel_relaxed(0, event_base + TIMER_CLEAR); 164 writel_relaxed(0, event_base + TIMER_CLEAR);
169 writel_relaxed(~0, event_base + TIMER_MATCH_VAL); 165 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
@@ -201,7 +197,7 @@ static void __init msm_timer_init(void)
201 clockevents_register_device(ce); 197 clockevents_register_device(ce);
202err: 198err:
203 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); 199 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
204 res = clocksource_register_hz(cs, DGT_HZ >> MSM_DGT_SHIFT); 200 res = clocksource_register_hz(cs, dgt_hz);
205 if (res) 201 if (res)
206 pr_err("clocksource_register failed\n"); 202 pr_err("clocksource_register failed\n");
207} 203}