diff options
author | Stepan Moskovchenko <stepanm@codeaurora.org> | 2010-12-01 22:25:14 -0500 |
---|---|---|
committer | David Brown <davidb@codeaurora.org> | 2011-01-21 18:27:54 -0500 |
commit | a81c8c38ed06c5f59d62a2257d21ed02d2af38fe (patch) | |
tree | 25c6599ed9e5d54079e5af79766df52d6c012c66 /arch/arm/mach-msm | |
parent | b83ce5812a1581655df8d1502398f03408539ba5 (diff) |
msm: timer: Timer support for MSM8960
Modify the macros in the MSM timer driver to support the
MSM8960 chip.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm')
-rw-r--r-- | arch/arm/mach-msm/timer.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 5548b156cff9..e7f8e5a4d48f 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c | |||
@@ -55,7 +55,8 @@ enum timer_location { | |||
55 | #if defined(CONFIG_ARCH_QSD8X50) | 55 | #if defined(CONFIG_ARCH_QSD8X50) |
56 | #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ | 56 | #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ |
57 | #define MSM_DGT_SHIFT (0) | 57 | #define MSM_DGT_SHIFT (0) |
58 | #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) | 58 | #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \ |
59 | defined(CONFIG_ARCH_MSM8960) | ||
59 | #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ | 60 | #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ |
60 | #define MSM_DGT_SHIFT (0) | 61 | #define MSM_DGT_SHIFT (0) |
61 | #else | 62 | #else |
@@ -214,7 +215,7 @@ static void __init msm_timer_init(void) | |||
214 | } else if (cpu_is_qsd8x50()) { | 215 | } else if (cpu_is_qsd8x50()) { |
215 | msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; | 216 | msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; |
216 | msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; | 217 | msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; |
217 | } else if (cpu_is_msm8x60()) { | 218 | } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { |
218 | msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; | 219 | msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; |
219 | msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; | 220 | msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; |
220 | 221 | ||